Author's Latest Posts


Rebalancing Test And Yield In IC Manufacturing


Balancing yield and test is essential to semiconductor manufacturing, but it's becoming harder to determine how much weight to give one versus the other as chips become more specialized for different applications. Yield focuses on maximizing the number of functional chips from a production batch, while test aims to ensure that each chip meets rigorous quality and performance standards. And w... » read more

Big Changes Ahead For Photomask Technology


The move to curvilinear shapes on photomasks is gaining steam after years of promise as a way of improving yield, lowering defectivity, and reducing wasted space on a die — all of which are essential for both continued scaling and improved reliability in semiconductors. Interest in this approach ran high at this year's SPIE Photomask Technology + EUV Lithography Conference. Put simply, cur... » read more

Wirebonding Is Here To Stay


Few technologies in semiconductor manufacturing have stood the test of time as steadfastly as wirebonding. This process, which involves electrically connecting semiconductor devices to their packages, has been a cornerstone of the electronics industry since the beginning of the electronics industry. Like everything else in the semiconductor market, wirebonding technologies have changed over ... » read more

Integration Challenges For ATE Data


Tighter integration of automatic test equipment (ATE) into semiconductor manufacturing, so that data from one process can be seamlessly leveraged by another, holds significant promise to boost manufacturing efficiency and yield. The challenge is selling this concept to fabs, packaging houses, and their customers. Data involving yield parameters, process variations, and intricate details abou... » read more

Fab And Field Data Transforming Manufacturing Processes


The ability to capture, process, and analyze data in the field is transforming semiconductor metrology and testing, providing invaluable insight into a product's performance in real-time and under real-world conditions and use cases. Historically, data that encapsulates parameters such as power consumption, temperature, voltages, currents, timing, and other characteristics, was confined to d... » read more

Week In Review: Manufacturing, Test


Bosch completed its acquisition of TSI Semiconductors to expand its SiC chips business, reports Reuters. In April, Bosch announced plans to invest $1.5 billion in the Roseville, California, foundry to convert TSI’s manufacturing facilities into state-of-the-art processes, with the first SiC chips due out in 2026. Bosch CEO Stefan Hartung said the full expansion "depends on the support of the... » read more

High-NA EUV Progress And Problems


High-NA EUV will enable logic scaling for at least the next couple process nodes. It’s complex, expensive, and a feat of optical engineering, but there are a lot of components with mixed progress. Harry Levinson, principal lithographer at HJL Lithography, talks  about when this technology will likely show up, what problems still need to be resolved, and what comes next. Related Readin... » read more

Week In Review: Semiconductor Manufacturing, Test


Intel dropped out of a $5.4 billion deal to purchase Tower Semiconductor in Israel. Intel cited the inability to obtain regulatory approval in a timely manner as the reason for ending the deal signed in February. Intel will pay a $353 million termination fee to Tower. The silicon wafer supply has moved back into positive territory for 2023 thanks to a 7% decline in wafer shipments combined w... » read more

Directed Self-Assembly Finds Its Footing


Ten years ago, when the industry was struggling to deliver EUV lithography, directed self-assembly (DSA) roared to the forefront of research and development for virtually every manufacturer determined to extend the limits of 193i. It was the hot topic at of the 2012 SPIE Advanced Lithography Conference, with one attendee from Applied Materials comparing its potential to disrupt the industry to ... » read more

Navigating the Metrology Maze For GAA FETs


The chip industry is pushing the boundaries of innovation with the evolution of finFETs to gate-all-around (GAA) nanosheet transistors at the 3nm node and beyond, but it also is adding significant new metrology challenges. GAA represents a significant advancement in transistor architecture, where the gate material fully encompasses the nanosheet channel. This approach allows for the vertical... » read more

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