Author's Latest Posts


Ensuring Reliability Becomes Harder In Multi-Die Assemblies


Multi-die assemblies are bringing together a variety of materials and processes with distinctly different physical properties, creating significant challenges in manufacturing and packaging that can impact yield at time zero and reliability in the field. What passes electrical screening at the end of the line may look good on paper, but these devices can still fail once exposed to rapid and ... » read more

Digital Twins For Packaging: Bridging Design, Fab, Test, And Reliability


Digital twins dominated discussions at SEMICON West this year, appearing in keynote presentations, panel sessions, and workshops. The conversation reflected a noticeable shift in how the industry views the technology. What once was mainly associated with design exploration now spans the manufacturing lifecycle. In packaging and assembly, digital twins are emerging as a way to connect design ... » read more

Metrology’s Growing Role In Reducing False Defects


When a good die fails test and gets scrapped, often no one notices, because false failures look identical to real ones. Yet across the industry, these phantom defects are quietly eroding yield, inflating test costs, and masking the true health of manufacturing processes. At advanced nodes and in heterogeneous packaging, where margins are already razor-thin, even minor variations in contact r... » read more

Smarter Packaging: How AI is Reshaping Assembly and Materials Control


When a multi-die package worth $500 fails final test because of a defect that originated three process steps earlier, the economics of advanced packaging become painfully clear. Each excursion carries downstream costs that ripple across assembly, final test, and even system qualification. As packaging margins tighten, the industry is betting on artificial intelligence (AI) to catch those pro... » read more

Precision Under Pressure: Managing Materials Complexity In Advanced Packaging


In the race to extend Moore's Law through advanced packaging, the limits of precision are no longer defined solely by lithography. Increasingly, they are dictated by the unpredictable behavior of materials. Semiconductor packaging today is no longer limited to just silicon and copper. It includes an expanding range of polymers, adhesives, dielectrics, exotic metals, along with substrates suc... » read more

The Hidden Cost Of Contact Resistance


Contact resistance, or CRES, is one of those problems that most engineers prefer not to think about until it's staring them in the face. For years, it could be managed quietly with routine probe card cleaning or a scheduled socket swap. That approach worked well enough when pin counts were lower and devices pulled less current, but the ground has shifted since then. Today’s AI processors m... » read more

How Semiconductor Fabs Use Water


Water — lots of it — is a critical enabler for advanced chip architectures, lithography, and back-end packaging. It feeds the ultra-pure water loops that touch every wafer, sluicing heat out of tools that run hotter at each node, and carrying spent chemistries to treatment. The natural reaction to reports that fabs “use millions of gallons of water” is concern, but the engineering re... » read more

Manufacturing At The Limits


Hybrid bonding has been in production for several years, with mature flows capable of delivering robust yields using 10µm interconnects. At that scale, processes can tolerate hundreds of nanometers of overlay variation, modest differences in wafer bow, and particle sizes rivaling the interconnect height without catastrophic impact. Hybrid bonding is compatible with optical metrology, existing ... » read more

Metrology Under Pressure: Detecting Defects in Fine-Pitch Hybrid Bonding


As advanced packaging pushes deeper into the sub-10µm realm, traditional inspection and metrology systems are being forced to evolve with it. Hybrid bonding, a critical enabler of vertical integration and 3D system performance, relies on exceptionally tight alignment and defect-free bonding surfaces. But as interconnect pitch shrinks, even nanometer-scale variations in height, tilt, or cont... » read more

CMOS 2.0: Layered Logic For The Post-Nanosheet Era


The semiconductor industry has relied on a simple equation for more than five decades — shrink the transistor, pack more onto every wafer, and watch performance soar as costs plummet. While each new node delivered predictable gains in speed, power efficiency, and density, that formula is rapidly running out of steam. As transistors approach single-digit nanometer processes, manufacturing c... » read more

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