Manufacturing At The Limits

By Gregory Haley - 21 Aug, 2025 - Comments: 2

Hybrid bonding has been in production for several years, with mature flows capable of delivering robust yields using 10µm interconnects. At that scale, processes can tolerate hundreds of nanometers of overlay variation, modest differences in wafer bow, and particle sizes rivaling the interconnect height without catastrophic impact. Hybrid bonding is compatible with optical metrology, existing ... » read more

Metrology Under Pressure: Detecting Defects in Fine-Pitch Hybrid Bonding

By Gregory Haley - 12 Aug, 2025 - Comments: 1

As advanced packaging pushes deeper into the sub-10µm realm, traditional inspection and metrology systems are being forced to evolve with it. Hybrid bonding, a critical enabler of vertical integration and 3D system performance, relies on exceptionally tight alignment and defect-free bonding surfaces. But as interconnect pitch shrinks, even nanometer-scale variations in height, tilt, or cont... » read more

CMOS 2.0: Layered Logic For The Post-Nanosheet Era

By Gregory Haley - 24 Jul, 2025 - Comments: 0

The semiconductor industry has relied on a simple equation for more than five decades — shrink the transistor, pack more onto every wafer, and watch performance soar as costs plummet. While each new node delivered predictable gains in speed, power efficiency, and density, that formula is rapidly running out of steam. As transistors approach single-digit nanometer processes, manufacturing c... » read more

How Advanced Packaging Is Reshaping Inspection

By Gregory Haley - 10 Jul, 2025 - Comments: 0

As semiconductor devices continue advancing into more sophisticated packaging schemes, traditional optical inspection technologies are brushing up against physical and computational boundaries. The growing reliance on 2.5D and 3D integration, hybrid bonding, and wafer-level processes has made it much harder to detect defects consistently and early enough to protect yields. While optical insp... » read more

Disruptive Changes Ahead For Photomasks?

By Gregory Haley - 25 Jun, 2025 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down with four experts to explore the current state and future direction of mask-making, with insights from Harry Levinson, principal lithographer at HJL Lithography; Aki Fujimura, CEO of D2S; Ezequiel Russell, senior director of mask technology at Micron; and Christopher Progler, executive vice president and CTO at Photronics. What follows ... » read more

Power Delivery Challenges For AI Chips

By Gregory Haley - 19 Jun, 2025 - Comments: 0

As artificial intelligence (AI) workloads grow larger and more complex, the various processing elements being developed to process all that data are demanding unprecedented levels of power. But delivering this power efficiently and reliably, without degrading signal integrity or introducing thermal bottlenecks, has created some of the toughest design and manufacturing challenges in semiconducto... » read more

Photomask Changes And Challenges At Mature And Advanced Nodes

By Gregory Haley - 16 Jun, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the current state and future direction of mask-making, with Harry Levinson, principal lithographer at HJL Lithography; Aki Fujimura, CEO of D2S; Ezequiel Russell, senior director of mask technology at Micron; and Christopher Progler, executive vice president and CTO at Photronics. What follows are excerpts of that conversation.... » read more

Rethinking Chip Reliability For Harsh Conditions

By Gregory Haley - 10 Jun, 2025 - Comments: 0

As semiconductors push into environments once considered untenable, reliability expectations are being redefined. From the vacuum of space and the inside of jet engines to deep industrial automation and electrified drivetrains, chips now must endure extreme temperature swings, corrosive atmospheres, mechanical vibration, radiation, and unpredictable power cycles, all while delivering increasing... » read more

On The Ground At ECTC 2025

By Gregory Haley - 02 Jun, 2025 - Comments: 0

Senior Executive Editor Laura Peters examines the the hot topics at last week's IEEE's Electronic Components and Technology Conference, including the impact of hardware-software integration on power consumption, co-packaged optics, hybrid bonding, and fan-out panel-level packaging. https://youtu.be/yBDKqrPQBl4 » read more

Inside Chips Podcast: May 27

By Gregory Haley - 27 May, 2025 - Comments: 0

Jo De Boeck, chief strategy officer and EVP at imec, talks with Semiconductor Engineering Technology Editor Gregory Haley about system technology co-optimization and the intersection of technology and AI. https://www.youtube.com/watch?v=XUgQPBIaDHQ » read more

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