Guy Cortez

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Guy Cortez is product management, principal, at Synopsys. His marketing career spans more than 25 years. He has held various marketing positions, including technical, product/solution, channel/field, integrated/corporate, alliance and business development for companies such as Synopsys, Cadence, VMware and Optimal+. Prior to that, Cortez spent 12 years as a test engineer at Hughes Aircraft Company (now Boeing), and later at Sunrise Test Systems (which became Viewlogic, and later Synopsys). At Hughes, he was responsible for generating all of the manufacturing test programs for the ASICs developed in the Missile Systems Group Division. At Sunrise, Cortez was a pre and post-sales applications engineer, and also doubled as the company’s instructor.

Author's Latest Posts

Reducing Design Margins With Silicon Model Calibration
By Guy Cortez - 09 Jul, 2024 - Comments: 0

By Guy Cortez and Mark Laird It’s no secret to anyone that chip design gets harder every year. There are two major trends driving these ever-increasing challenges. The first is the continual scaling down to smaller design nodes. Although the pace of new node introduction has slowed somewhat in recent years, the impact of each new geometry and process is more dramatic than ever before. Acce... » read more

SLM Analytics Of In-Chip Monitor Data Unlock Greater Productivity And Cost Savings
By Guy Cortez - 09 Jan, 2024 - Comments: 0

When it comes to measuring key operational metrics such as power and performance of your silicon, in-chip monitors have been the longstanding cornerstone for providing such valuable measurements and insights. Data captured from these monitors – process monitors configured in the form of ring oscillator chains being the most common – can tell you if your chip is meeting the requisite power o... » read more

Silicon Lifecycle Management Advances With Unified Analytics
By Guy Cortez - 25 Apr, 2023 - Comments: 0

In a typical day in the life of a product engineer, they have gone through the requisite wafer sort testing in manufacturing with the next step to assemble the resultant good die into their respective packages. While performing a series of parametric tests during final test, yield issues are encountered and the process of finding the source of the issues begins. Luckily, with access to a good d... » read more

Debug And Traceability Of MCMs And Chiplets In The Manufacturing Test Process
By Guy Cortez - 16 Apr, 2021 - Comments: 0

Single die packages and products have been the norm for decades. Moreover, so has multi-chip modules (MCMs) or system in package (SiP) for quite some time. Understandably, with ASICs and SoCs becoming larger while silicon geometries continue to get smaller, there is an opportunity to combine even more functionality into a smaller form factor for the end product. Hence, new advancements in desig... » read more

Finally, Analyzing All Test And Manufacturing Data Automatically
By Guy Cortez - 09 Mar, 2021 - Comments: 0

Product quality and yield, operational efficiency, and time-to-market continue to be dominant drivers in the semiconductor industry. Adding to this complexity is a diverse manufacturing and test supply-chain of independent providers all continuously generating enormous amounts of different types of chip-related data in various formats. The knowledge contained within this data is critical to pro... » read more

Is It Safe To Assume That All “Passed” Die Are Actually “Good” Die?
By Guy Cortez - 09 Oct, 2017 - Comments: 0

In a world where Quality and Brand Protection is King, as certainly is the case for the automotive and medical device industries where strict minimal DPPM (defective parts per million) requirements are a common constraint, new methods for “escape” prevention and outlier detection are constantly being evaluated and implemented by semiconductor vendors to prevent any defective or marginal par... » read more

Are All Known Good Tested Devices Created Equal?
By Guy Cortez - 10 Jul, 2017 - Comments: 0

Your known good parts all had passed their required wafer sort, final test, and system-level tests and were shipped to your customers. However, as we all know, a known good part or device sometimes does not stay good and may end up failing prematurely in the field and flagged as an RMA (return material authorization) by your customer. But why is it that some good parts fail early and others las... » read more

A More Efficient Way To Calculate Device Specs Of Thousands Of Tests For Improved Quality And Yield
By Guy Cortez - 05 Jun, 2017 - Comments: 0

Today’s devices are required to pass thousands of parametric tests prior to being shipped to customers. A key challenge test engineers face, in addition to optimizing the number of tests they run on the device, is how to quickly and accurately define the true specification limits that should be used to determine if the device is “good”. Device specification limits that are too wide may... » read more

Finally, Realizing The Full Benefits Of Parallel Site-To-Site (S2S) Testing
By Guy Cortez - 08 May, 2017 - Comments: 0

A very common and well-known practice by manufacturers during the IC test process is to test as many of the device die or packaged parts as possible in parallel (i.e. sites) during wafer sort and final test in order to increase test time efficiency and lower overall test costs. The constraints that typically restrict how many test sites can be used at any given time are the design I/O and capac... » read more

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