Alternative Text

Jesse Allen

  (all posts)
Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Research Bits: June 9
By Jesse Allen - 09 Jun, 2025 - Comments: 0

InGaOx GAA transistor Researchers from the University of Tokyo created a gate-all-around transistor made from gallium-doped indium oxide (InGaOx). Doping indium oxide with gallium suppressed oxygen vacancies, improving transistor reliability. "We wanted our crystalline oxide transistor to feature a 'gate-all-around' structure, whereby the gate, which turns the current on or off, surrounds t... » read more

Blog Review: June 4
By Jesse Allen - 04 Jun, 2025 - Comments: 0

In a podcast, Siemens’ Conor Peick, Dale Tutt, and Mike Ellow chat about the implications of the software-defined transition, how it affects semiconductor development, and why it seems to be leading more companies towards developing their own silicon. Cadence’s Vinod Khera shows off a Linux-based audio development platform for prototyping AI audio applications with support for real-time ... » read more

Research Bits: June 3
By Jesse Allen - 03 Jun, 2025 - Comments: 0

Imaging power electronics Researchers from the Institute of Science Tokyo, Harvard University, and Hitachi used diamond quantum sensors to analyze the magnetization response of soft magnetic materials used in power electronics. The method can simultaneously image both the amplitude and phase of AC stray fields over a wide frequency range up to 2.3 MHz. It uses a diamond quantum sensor with ... » read more

Blog Review: May 28
By Jesse Allen - 28 May, 2025 - Comments: 0

Siemens’ Patrick Hope considers how to fully perform post-route signal integrity verification on PCB designs while maintaining the project’s timeline by implementing a progressive verification methodology that enables signal integrity experts to focus on issues that demand their expertise rather than simple errors. Cadence’s Vanessa Do checks out how CXL addresses the constant demand f... » read more

Research Bits: May 27
By Jesse Allen - 27 May, 2025 - Comments: 0

Tracking ferroelectric domain walls Researchers from Oak Ridge National Laboratory and National Cheng Kung University developed a technique called scanning oscillator piezoresponse force microscopy to observe how domain walls move in ferroelectric materials under rapidly fluctuating electric fields. “Domain walls can have completely different properties from the neighboring domains they s... » read more

Blog Review: May 21
By Jesse Allen - 21 May, 2025 - Comments: 0

Synopsys’ Frank Malloy listens in on a panel discussing the engineering challenges introduced by multi-die designs, from multi-physics interactions that impact power and thermal integrity to the availability of multi-die packages and industry standards. Siemens’ Bruce Caryl shows how to determine how much a design’s power delivery network is contributing to jitter on the output drivers... » read more

Research Bits: May 20
By Jesse Allen - 20 May, 2025 - Comments: 0

Smart t-shirt with sound waves Researchers at ETH Zurich developed a smart textile that uses acoustic waves passed through glass fibers to measure touch, pressure, and movement. The researchers said that using acoustic waves rather than electronics makes measurements more precise with low power consumption and the textiles lighter, more breathable, and easier to wash. It also uses readily avai... » read more

Blog Review: May 14
By Jesse Allen - 14 May, 2025 - Comments: 0

Siemens’ Stephen V. Chavez finds that proper PCB high voltage spacing between conductive elements is key to reliability and understanding the principles of clearance (through-air spacing) and creepage (along-surface spacing) is critical. Cadence’s Frank Ferro checks out how the new HBM4 standard boosts bandwidth and addresses key issues in the data center, including the growing size of L... » read more

Research Bits: May 13
By Jesse Allen - 13 May, 2025 - Comments: 0

Benchmarking 3D-IC cooling Researchers from Massachusetts Institute of Technology (MIT) and HRL Laboratories developed a specialized chip to test and validate cooling solutions for packaged chip stacks. The chip dissipates extremely high power, generating heat through the silicon layer and in localized hot spots to mimic high-performance logic chips. It then uses diodes to measure temperatu... » read more

Blog Review: May 7
By Jesse Allen - 07 May, 2025 - Comments: 0

Cadence’s Mayank Bhatnagar examines the challenge of ensuring the functional safety of disaggregated designs and how UCIe can serve as a certified way to connect individual components. Siemens’ Charlie Olson explores the causes of inter-domain leakage when a DC path is formed between two power rails and how to overcome the limitations of traditional electrical rule checking. Synopsys�... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy