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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Blog Review: Jan. 11
By Jesse Allen - 11 Jan, 2017 - Comments: 0

Mentor's Ron Press examines why test hasn't become a bottleneck in creating ever more advanced semiconductors. Synopsys' Graham Etchells warns that while finFET technologies have been successful, challenges persist. Cadence's Paul McLellan shares a behind-the-scenes look at developing the Palladium Z1 emulator. The White House's Craig Mundie and Paul Otellini highlight a PCAST report o... » read more

Power/Performance Bits: Jan. 10
By Jesse Allen - 10 Jan, 2017 - Comments: 0

Antiferromagnetic magnetoelectric RAM Researchers at Helmholtz-Zentrum Dresden-Rossendorf (HZDR), Swiss Nanoscience Institute, and the University of Basel developed a concept for a new, low power memory chip. In particular, the group focused on finding an alternative to MRAM using magnetoelectric antiferromagnets, which are activated by an electrical voltage rather than by a current. "... » read more

The Week In Review: Design
By Jesse Allen - 06 Jan, 2017 - Comments: 0

IP Arastu Systems uncorked a LPDDR3 DRAM Memory Controller. The controller is fully compliant with JEDEC standard JESD209-3C and supports various power down modes as well as multiple channels with a privilege to configure and manage each channel independently and parameterized data width. CSEM's Bluetooth Low Energy silicon RF IP has been validated as Bluetooth 5 compatible. RF test equip... » read more

Blog Review: Jan. 4
By Jesse Allen - 04 Jan, 2017 - Comments: 0

Mentor's Harry Foster wraps up his functional verification study series with a look the impact of verification maturity and safety critical designs on first silicon success. Synopsys' David Benas argues for using the insurance industry as a model in assessing the risk of potential software flaws. Cadence's Tom Anderson shares highlights from the recent International Workshop on Microproce... » read more

Power/Performance Bits: Jan. 3
By Jesse Allen - 03 Jan, 2017 - Comments: 0

Paper-based bacteria battery Researchers at Binghamton University, State University of New York have created a bacteria-powered battery on a single sheet of paper that can power disposable electronics. The manufacturing technique reduces fabrication time and cost, and the design could revolutionize the use of bio-batteries as a power source in remote, dangerous and resource-limited areas. ... » read more

Power/Performance Bits: Dec. 27
By Jesse Allen - 27 Dec, 2016 - Comments: 0

Tiny diamond radio Researchers at Harvard built the world's smallest radio receiver, built out of an assembly of atomic-scale defects in pink diamonds. The radio uses tiny imperfections in diamonds called nitrogen-vacancy (NV) centers. To make NV centers, researchers replace one carbon atom in a diamond crystal with a nitrogen atom and remove a neighboring atom -- creating a system that i... » read more

The Week In Review: Design
By Jesse Allen - 23 Dec, 2016 - Comments: 0

M&A ARM reached further into the HPC space with its acquisition of Allinea Software, a provider of debug and performance analysis tools for HPC systems. Currently, 80% of the world's top 25 supercomputers use Allinea's tools, and ARM will continue supporting multiple processor architectures. Terms of the deal were not disclosed. PLDA Group is spinning out its QuickPlay C/C++ tool for ... » read more

Blog Review: Dec. 21
By Jesse Allen - 21 Dec, 2016 - Comments: 0

Mentor's Jeff Miller and ARM's Nandan Nayampally contend that it's easier than ever to design custom SoCs. Cadence's Paul McLellan provides a basic primer on silicon photonics, from a presentation by Gilles Lamant. The US Department of Transportation is considering requiring the inclusion of vehicle-to-vehicle communication in new cars, says Synopsys' Robert Vamosi. Applied's Shekar Kr... » read more

Power/Performance Bits: Dec. 20
By Jesse Allen - 20 Dec, 2016 - Comments: 0

Stamping with electronic ink Engineers at MIT fabricated a stamp made from carbon nanotubes that is able to print electronic inks onto rigid and flexible surfaces. The team's stamping process should be able to print transistors small enough to control individual pixels in high-resolution displays and touchscreens, said A. John Hart, associate professor of contemporary technology and mecha... » read more

The Week In Review: Design
By Jesse Allen - 16 Dec, 2016 - Comments: 0

IP eSilicon launched 14nm FinFET and 28nm planar HBM Gen2 Hardened PHY. It supports up to 256Gbytes/sec bandwidth with 8x128b channels at 2Gbps per I/O, and the integrated I/O supports up to 2Gbps DDR operation across a 4mm interposer channel. The PHY was developed on Samsung 14LPP and TSMC 28HPC technologies. Flex Logix designed a high-performance embedded FPGA IP core for TSMC 16FF+ and... » read more

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