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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

The Week In Review: Design
By Jesse Allen - 28 Oct, 2016 - Comments: 0

IP ARM unveiled a suite of products focused on the IoT, with new processors, radio technology, subsystems, end-to-end security and a cloud-based services platform. Included are Cortex-M23 and Cortex-M33, the first embedded processors based on the ARMv8-M architecture. The Cortex-M33 features configuration options including a coprocessor interface, DSP and floating point computation, while th... » read more

Blog Review: Oct. 26
By Jesse Allen - 26 Oct, 2016 - Comments: 0

Synopsys' Robert Vamosi provides some additional information on last Friday's massive DDoS attack against DNS provider Dyn, which hampered access to many big-name websites. On the same note, Cadence's Paul McLellan warns of the hazards default and easy-to-guess device passwords present to people far beyond the original user. Mentor's Arvind Narayanan warns that the 10nm era has changed ph... » read more

Power/Performance Bits: Oct. 25
By Jesse Allen - 25 Oct, 2016 - Comments: 0

Energy-harvesting floor Engineers at the University of Wisconsin-Madison developed a flooring material which can be used as a triboelectric nanogenerator to convert footsteps into electricity. The method uses wood pulp, a common waste material already often used in flooring. The pulp is partly make of cellulose nanofibers, which when chemically treated produce an electrical charge when th... » read more

The Week In Review: Design
By Jesse Allen - 21 Oct, 2016 - Comments: 0

Tools Mentor Graphics added RF verification capabilities for wireless applications in the connected sensor and IoT markets to its Tanner design and layout suite. Mentor also integrated its Questa verification tool with the open-source Jenkins Continuous Integration and Source Code Management (CI/SCM) ecosystem. The plugin, a free download, gives Jenkins the ability to utilize regression run ... » read more

Blog Review: Oct. 19
By Jesse Allen - 19 Oct, 2016 - Comments: 0

Mentor's Colin Walls provides some tips on writing portable, reusable code. Cadence's Christine Young contends that you should never use 2.5D for characterization at advanced nodes. Synopsys' Eric Huang considers one impractical use of USB heating and the IoT. Applied's Ben Lee predicts a rapid growth in China's power device manufacturing. NXP's Joppe Bos digs into the challenges of... » read more

Power/Performance Bits: Oct. 18
By Jesse Allen - 18 Oct, 2016 - Comments: 0

Speeding up memory with T-rays Scientists at the Moscow Institute of Physics and Technology (MIPT), the University of Regensburg in Germany, Radboud University Nijmegen in the Netherlands, and Moscow Technological University proposed a way to improve the performance of memory through using T-waves, or terahertz radiation, as a means of resetting memory cells. This process is several thousand... » read more

The Week In Review: Design
By Jesse Allen - 14 Oct, 2016 - Comments: 0

M&A Mentor Graphics acquired Galaxy Semiconductor, a provider of test data analysis and defect reduction software ranging from initial characterization of sample devices to automated yield management of large-scale production. The Galway, Ireland company was founded in 1998. Terms of the deal were not disclosed. IP Imagination rolled out a new heterogeneous MIPS CPU with many core/... » read more

Blog Review: Oct. 12
By Jesse Allen - 12 Oct, 2016 - Comments: 0

Mentor's Harry Foster digs into verification technology adoption trends for ASIC/IC. Cadence's Tom Anderson looks at the goals of the Portable Stimulus Working Group and how they compare to those of UVM. Synopsys' Eric Huang checks out what's new in the land of USB, Type-C adoption, and cable testing. Ansys' Aveek Sarkar explores the challenges facing 7nm designs and the benefits of ch... » read more

Power/Performance Bits: Oct. 11
By Jesse Allen - 11 Oct, 2016 - Comments: 2

Getting to 1nm Researchers at the Lawrence Berkeley National Laboratory, UC Berkeley, University of Texas at Dallas, and Stanford University created a transistor with a working 1nm gate from carbon nanotubes and molybdenum disulfide (MoS2). "The semiconductor industry has long assumed that any gate below 5 nanometers wouldn't work, so anything below that was not even considered," said fir... » read more

The Week In Review: Design
By Jesse Allen - 07 Oct, 2016 - Comments: 0

Tools Synopsys updated RSoft, its software for the design of photonic devices. The updates include increased integration with the company's TCAD products as well as faster simulations and additional ways to customize photonic device analysis. IP Mentor Graphics, Northwest Logic, and Krivi Semiconductor collaborated on DDR4 SDRAM IP to integrate design and verification into a single flo... » read more

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