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Jesse Allen

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Jesse Allen is the Knowledge Center administrator and a senior editor at Semiconductor Engineering.

Author's Latest Posts

Blog Review: June 26
By Jesse Allen - 26 Jun, 2024 - Comments: 0

Cadence's Neelabh Singh examines the Gen4 link recovery mechanism in USB4 Version 2.0, an autonomous process that is initiated by a router when it encounters uncorrectable error events, and identified verification challenges. Synopsys' Gary Ruggles and Priyank Shukla highlight improvements to PCIe 7.0 that will enable secure data transfers and boost bandwidth for the next generation of AI an... » read more

Blog Review: June 19
By Jesse Allen - 19 Jun, 2024 - Comments: 0

Siemens' John McMillan and Todd Burkholder suggest using an automatic formal-based approach to verifying chiplet package connections early in the design process. Cadence's Veena Parthan explores the intricacies of wind tunnel testing in automotive design and how the collaborative relationship between computational fluid dynamics (CFD) and wind tunnels has resulted in accelerated and more nua... » read more

Research Bits: June 18
By Jesse Allen - 18 Jun, 2024 - Comments: 0

Gallium nitride can take the heat Researchers from Massachusetts Institute of Technology (MIT), the UAE's Technology Innovation Institute, Ohio State University, Rice University, and Bangladesh University of Engineering and Technology investigated the performance of ohmic contacts in a gallium nitride (GaN) device at extremely high temperatures, such as those that would be required for devices... » read more

Blog Review: June 12
By Jesse Allen - 12 Jun, 2024 - Comments: 0

Cadence's Deep Mehta finds that PCIe 6.0 switches need advanced verification strategies that delve deeper than basic functionality, such as generating backpressure traffic to identify potential performance bottlenecks and ensure the switch operates optimally in real-world scenarios. Siemens' Reetika explains why proper management and verification of reset domain crossing (RDC) paths are cruc... » read more

Blog Review: June 5
By Jesse Allen - 05 Jun, 2024 - Comments: 0

Cadence's Neelabh Singh provides an overview of the low power entry and exit flows in USB4 Version 2.0 link speed and how they have been simplified by making low power entry uni-directional and removing the need for certain handshakes for low power exit of the re-timers. In a podcast, Siemens' Steph Chavez chats with Daniel Beeker of NXP about the foundational importance of power distributio... » read more

Research Bits: June 4
By Jesse Allen - 04 Jun, 2024 - Comments: 0

Ultra-pure silicon Researchers from the University of Manchester and University of Melbourne developed a technique to engineer ultra-pure silicon that could be used in the construction of high-performance qubit devices that extend quantum coherence times. The highly purified silicon chips house and protect the qubits so they can sustain quantum coherence much longer, enabling complex calcul... » read more

Research Bits: May 28
By Jesse Allen - 28 May, 2024 - Comments: 0

Nanofluidic memristive neural networks Engineers from EPFL developed a functional nanofluidic memristive device that relies on ions, rather than electrons and holes, to compute and store data. “Memristors have already been used to build electronic neural networks, but our goal is to build a nanofluidic neural network that takes advantage of changes in ion concentrations, similar to living... » read more

Blog Review: May 22
By Jesse Allen - 22 May, 2024 - Comments: 0

Cadence's Sree Parvathy introduces Verilog-A, a high-level language that uses modules to describe the structure and behavior of analog systems and enables the top-down system to be defined before the actual transistor circuits are assembled. Siemens' Keith Felton suggests the process of package substrate design is improved by leveraging the collective expertise of multiple design domain spec... » read more

Research Bits: May 21
By Jesse Allen - 21 May, 2024 - Comments: 0

Lithium tantalate PICs Researchers at EPFL and Shanghai Institute of Microsystem and Information Technology developed scalable photonic integrated circuits (PICs) based on lithium tantalate (LiTaO3). Lithium tantalate can provide excellent electro-optic qualities and is used in telecom 5G RF filters. The team developed a wafer-bonding method for lithium tantalate, which is compatible with s... » read more

Blog Review: May 15
By Jesse Allen - 15 May, 2024 - Comments: 0

Cadence's Anika Sunda suggests that RISC-V has opened numerous doors for innovation and believes EDA tools can help bridge the knowledge gap and foster a growing community of RISC-V developers. Synopsys' Alessandra Costa chats with industry experts about challenges facing analog design, what's needed for multi-die designs, and the potential of AI. Siemens' Bill Ji explains why understandi... » read more

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