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Katherine Derbyshire

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Katherine Derbyshire is a technical editor at Semiconductor Engineering.

Author's Latest Posts

Coming To A Fab Near You?
By Katherine Derbyshire - 21 Jan, 2016 - Comments: 1

What do Quentin Tarantino and ASML have in common? Anamorphic lenses. The optical image created by an anamorphic lens is oval, rather than round, with different magnifications along the horizontal and vertical axes. Tarantino used 65mm anamorphic lenses to film The Hateful Eight, and some theaters are also using them to screen the movie. It’s the first fiction feature to use this format s... » read more

The Next Resists…Continued
By Katherine Derbyshire - 17 Dec, 2015 - Comments: 1

As previously discussed, conventional chemically-amplified resists are struggling to balance the competing requirements of EUV lithography. Simultaneously meeting the industry’s targets for resolution, sensitivity, and line-edge roughness may require new resist concepts. Inpria’s resist technology, based on tin-oxide nano clusters, is one possibility. Recently published work at SUNY Albany ... » read more

Quantum Entanglement Test
By Katherine Derbyshire - 25 Nov, 2015 - Comments: 0

One of the more bizarre implications of quantum theory is the so-called “spooky action at a distance” effect. If two quantum particles are entangled, measuring the state of one simultaneously defines the state of the other, regardless of the distance between them. This behavior appears to defy the rule that nothing can travel faster than the speed of light: information regarding the stat... » read more

What’s Really Causing Line-Edge Roughness?
By Katherine Derbyshire - 19 Nov, 2015 - Comments: 0

As previously discussed, shot noise is an important contributor to line edge roughness. However, as the title of one paper on the subject put it, “Do not always blame the photons.” The line edge roughness of a chemically amplified resist ultimately depends on photoacid generation and the deprotection of the resist’s base monomers. Photons absorbed by the resist simply trigger a chain ... » read more

The Next Resists
By Katherine Derbyshire - 22 Oct, 2015 - Comments: 5

As EUV exposure tools, sources, and photomasks have become more capable, the lithography sector’s attention has turned to EUV photoresist. After all, once the exposure system can produce a high quality image at the wafer, the resist still has to capture it for pattern transfer. Unfortunately, the increasing emphasis on photoresist has made the limitations of current formulations even more obv... » read more

Resist Sensitivity, Source Power, And EUV Throughput
By Katherine Derbyshire - 30 Sep, 2015 - Comments: 0

In a recent article, I quoted 15 mJ/cm2 as the target sensitivity for EUV photoresists, and discussed the throughput that could be achieved at various source power levels. However, as a commenter on that article pointed out, reaching the 15 mJ/cm² target while also meeting line roughness requirements is itself a challenging problem. Because of the high energy of EUV photons, a highly sensitive... » read more

EUV: Cost Killer Or Savior?
By Katherine Derbyshire - 17 Sep, 2015 - Comments: 4

Moore’s Law, the economic foundation of the semiconductor industry, states that transistor density doubles in each technology generation, at constant cost. As IMEC’s Arindam Mallik explained, however, the transition to a new technology node is not a single event, but a process. Typically, when the new technology is first introduced, it brings a 20% to 25% wafer cost increase. Process opt... » read more

Reliability After Planar Silicon
By Katherine Derbyshire - 29 Jul, 2015 - Comments: 2

Negative bias temperature instability (NBTI) poses a very serious reliability challenge for highly scaled planar silicon transistors, as previously discussed. However, the conventional planar silicon transistor appears to be nearing the end of its life for other reasons, too. The mobility of carriers in silicon limits switching speed even as it becomes more difficult to maintain sufficient elec... » read more

Litho Challenges Break The Design-Process Wall
By Katherine Derbyshire - 22 Jun, 2015 - Comments: 3

The days when chip designers could throw tape “over the wall” to the manufacturing side are long gone. Over the last several technology generations, increasingly restrictive process kits have forced designers to accommodate their circuit structures to the manufacturing process. Lacking a successor to 193nm lithography, the industry has turned to increasingly complex resolution enhancemen... » read more

Can Copper Revolutionize Interconnects Again?
By Katherine Derbyshire - 10 Jun, 2015 - Comments: 2

Electromigration and resistivity present serious obstacles to interconnect scaling, as previously discussed. In a copper damascene process, grain growth is constrained by the narrow trenches into which copper is deposited. As the grain size approaches the mean free path of electrons in copper, electron scattering at sidewalls and grain boundaries increases and resistivity jumps. Meanwhile, incr... » read more

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