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Katherine Derbyshire

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Katherine Derbyshire is a technical editor at Semiconductor Engineering.

Author's Latest Posts

The Next Resists
By Katherine Derbyshire - 22 Oct, 2015 - Comments: 5

As EUV exposure tools, sources, and photomasks have become more capable, the lithography sector’s attention has turned to EUV photoresist. After all, once the exposure system can produce a high quality image at the wafer, the resist still has to capture it for pattern transfer. Unfortunately, the increasing emphasis on photoresist has made the limitations of current formulations even more obv... » read more

Resist Sensitivity, Source Power, And EUV Throughput
By Katherine Derbyshire - 30 Sep, 2015 - Comments: 0

In a recent article, I quoted 15 mJ/cm2 as the target sensitivity for EUV photoresists, and discussed the throughput that could be achieved at various source power levels. However, as a commenter on that article pointed out, reaching the 15 mJ/cm² target while also meeting line roughness requirements is itself a challenging problem. Because of the high energy of EUV photons, a highly sensitive... » read more

EUV: Cost Killer Or Savior?
By Katherine Derbyshire - 17 Sep, 2015 - Comments: 4

Moore’s Law, the economic foundation of the semiconductor industry, states that transistor density doubles in each technology generation, at constant cost. As IMEC’s Arindam Mallik explained, however, the transition to a new technology node is not a single event, but a process. Typically, when the new technology is first introduced, it brings a 20% to 25% wafer cost increase. Process opt... » read more

Reliability After Planar Silicon
By Katherine Derbyshire - 29 Jul, 2015 - Comments: 2

Negative bias temperature instability (NBTI) poses a very serious reliability challenge for highly scaled planar silicon transistors, as previously discussed. However, the conventional planar silicon transistor appears to be nearing the end of its life for other reasons, too. The mobility of carriers in silicon limits switching speed even as it becomes more difficult to maintain sufficient elec... » read more

Litho Challenges Break The Design-Process Wall
By Katherine Derbyshire - 22 Jun, 2015 - Comments: 3

The days when chip designers could throw tape “over the wall” to the manufacturing side are long gone. Over the last several technology generations, increasingly restrictive process kits have forced designers to accommodate their circuit structures to the manufacturing process. Lacking a successor to 193nm lithography, the industry has turned to increasingly complex resolution enhancemen... » read more

Can Copper Revolutionize Interconnects Again?
By Katherine Derbyshire - 10 Jun, 2015 - Comments: 2

Electromigration and resistivity present serious obstacles to interconnect scaling, as previously discussed. In a copper damascene process, grain growth is constrained by the narrow trenches into which copper is deposited. As the grain size approaches the mean free path of electrons in copper, electron scattering at sidewalls and grain boundaries increases and resistivity jumps. Meanwhile, incr... » read more

The End Of Silicon?
By Katherine Derbyshire - 04 May, 2015 - Comments: 1

As transistors shrink, not all device parameters scale at the same rate—and therein lies a potentially huge problem. In recent years, manufacturers have been able to reduce equivalent oxide thickness (EOT) more quickly than operating voltage. As a result, the electric field present in the channel and gate dielectric has been increasing. Moreover, EOT reduction is achieved in part by reduci... » read more

One-On-One: Dark Possibilities
By Katherine Derbyshire - 29 Apr, 2015 - Comments: 0

Professor Michael Taylor’s research group at UC San Diego is studying ways to exploit dark silicon to optimize circuit designs for energy efficiency. He spoke with Semiconductor Engineering about the post-Dennard scaling regime, energy efficiency from integrated circuits all the way up to data centers, and how the manufacturing side can help. What follows are excerpts of that conversation. (P... » read more

Sponges, Skyscrapers, And Low-K
By Katherine Derbyshire - 20 Apr, 2015 - Comments: 1

A sponge is a porous structure. So is a skyscraper. These two very different images exemplify the materials being considered for advanced low dielectric constant (κ) materials. Most porous dielectrics that have been tested up to this point resemble sponges. As Intel’s David Michalak explained at this month's Materials Research Society (MRS) Spring Meeting, these materials consist of a ba... » read more

One-On-One: Dark Servers
By Katherine Derbyshire - 14 Apr, 2015 - Comments: 1

Professor Michael Taylor’s research group at UC San Diego is studying ways to exploit dark silicon to optimize circuit designs for energy efficiency. He spoke with Semiconductor Engineering about the post-Dennard scaling regime, energy efficiency from integrated circuits all the way up to data centers, and how the manufacturing side can help. What follows are excerpts of that conversation. To... » read more

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