Mark LaPedus

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Mark LaPedus is Executive Editor for manufacturing at Semiconductor Engineering.

Author's Latest Posts

The Week In Review: Manufacturing
By Mark LaPedus - 07 Apr, 2017 - Comments: 0

Mask and fab equipment Seeking to speed up the semiconductor design and manufacturing process, D2S has rolled out its fifth-generation computational design platform (CDP). D2S, a supplier of GPU-accelerated computational systems or platforms, said the latest CDP is designed to enable faster simulations for a range of applications. Using Nvidia’s Pascal-based Tesla P40 GPUs, D2S’ fifth-... » read more

Inside Lithography And Masks
By Mark LaPedus - 05 Apr, 2017 - Comments: 3

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at [getentity id="22217" e_name="Imec"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; David Fried, chief technology officer at [getentity id="22210" e_name="Cove... » read more

Manufacturing Bits: April 4
By Mark LaPedus - 04 Apr, 2017 - Comments: 0

Open-source tomography software The University of Michigan, Cornell University and Kitware have developed an open-source software platform that enables three-dimensional imaging of nanomaterials. The open-source platform, dubbed Tomviz 1.0, enables researchers to image and process nanomaterials using electron tomography. Researchers can download the software. Using tomography, the software... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 31 Mar, 2017 - Comments: 0

Chipmakers At an event, Intel’s Technology and Manufacturing group outlined the company's vision. As part of the event, Intel reiterated what many are saying—the current node designations are meaningless and misleading. “For example, Intel estimates that its 14nm solution that has been out in the market since 2014 should be equal to 10nm solutions released by competitors in the near futu... » read more

Manufacturing Bits: March 28
By Mark LaPedus - 28 Mar, 2017 - Comments: 0

Dental implants Borrowing some of the same processes used in the semiconductor industry, the Peninsula Schools of Medicine and Dentistry and the University of Plymouth have developed new nanocoating materials for dental implants. Some three million Americans have dental implants, according to the American Academy of Implant Dentistry (AAID). This number is rising by 500,000 a year, accordin... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 24 Mar, 2017 - Comments: 0

Chipmakers China’s IC industry is embarking on a recruitment drive to prepare for the operation of new fabs in 2018, according to TrendForce. “TrendForce’s latest analysis on China’s semiconductor sector reveals that the country’s domestic IC manufacturers are affecting the movement of industry talent worldwide as they continue to aggressively headhunt for senior managers and enginee... » read more

Manufacturing Bits: March 21
By Mark LaPedus - 21 Mar, 2017 - Comments: 0

Making harder windows Using cubic silicon nitride materials, a team of researchers have developed a harder window that can sustain severe conditions. There is a demand for harder and stronger windows in various applications, such as engines, ball bearings, cutting tools and other others. To enable this technology, researchers used materials based on transparent polycrystalline ceramics. One... » read more

Patterning Problems Pile Up
By Mark LaPedus - 20 Mar, 2017 - Comments: 4

Chipmakers are ramping up 16nm/14nm finFET processes, with 10nm and 7nm now moving into early production. But at 10nm and beyond, chipmakers are running into a new set of problems. While shrinking feature sizes of a device down to 10nm, 7nm, 5nm and perhaps beyond is possible using current and future fab equipment, there doesn't seem to be a simple way to solve the edge placement error (EPE)... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 17 Mar, 2017 - Comments: 0

Chipmakers At this week’s TSMC Technology Symposium in San Jose, Calif., TSMC rolled out a dizzying array of new processes and technologies. Perhaps the most surprising announcement was a 22nm bulk CMOS process, which is geared for ultra low-power planar chips. The technology will compete against a 22nm FD-SOI technology from GlobalFoundries. Stay tuned. The battle has just begun. As e... » read more

Following Multiple Patterns
By Mark LaPedus - 16 Mar, 2017 - Comments: 2

The lithography market is in flux. Today, chipmakers plan to extend today’s 193nm immersion lithography and multi-patterning to at least 10nm and 7nm. For the most critical layers, though, it’s unclear if optical lithography can extend beyond 7nm. For that reason, chipmakers hope to insert extreme ultraviolet (EUV) lithography at 7nm and/or 5nm. To get a handle on the state of patterning, S... » read more

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