The Week In Review: Manufacturing

D2S’ new computational platform; packaging security; fan-out tool/materials boom.


Mask and fab equipment
Seeking to speed up the semiconductor design and manufacturing process, D2S has rolled out its fifth-generation computational design platform (CDP).

D2S, a supplier of GPU-accelerated computational systems or platforms, said the latest CDP is designed to enable faster simulations for a range of applications. Using Nvidia’s Pascal-based Tesla P40 GPUs, D2S’ fifth-generation CDP achieves 888 teraflops of processing speed, which is twice as fast as the previous-generation CDP from D2S.

The water-cooled CDP design is optimized for cleanroom manufacturing environments. The CDP can be used for the following applications:

Model-based mask data preparation (MB-MDP) for designing leading-edge photomasks with complex shapes. The CDP can simulate an entire mask plane (1.4 quintillion pixels).

Wafer plane analysis of mask images captured in scanning electron microscopy (SEM) systems to identify mask problems.

Inline thermal-effect correction of eBeam-based photomask writers to lower write times to an acceptable level.

Geometric checking and manipulation of curvilinear shapes on masks and wafers.

The latest application for D2S’ CDP is inline linearity correction for multi-beam mask writing. More specifically, the platform is expected to be used with NuFlare’s new MBM-1000 multi-beam mask writer. The CDP provides pixel-level dose correction to enhance the printability of masks incorporating more complex and smaller features.

All told, D2S’ GPU-based platforms have a competitive advantage over systems based on other architectures. “GPUs excel at simulating natural phenomena and work well in low latency situations, making them an ideal solution for advanced semiconductor manufacturing,” said Aki Fujimura, chief executive of D2S.

This, in turn, makes the technology ideal for the next wave of applications, such as EUV, ILT and multi-beam. “Seismic changes are underway in the photomask and semiconductor industry, prompting the need for greater simulation capability,” Fujimura said.

“Inverse lithography technology (ILT) and complex mask shapes, which are already being utilized in some leading-edge chip designs, will be increasingly needed as the industry migrates to smaller design nodes,” he said. “Significant progress is being made with multi-beam mask writing, which provides write times that are independent of shape count or complexity—making it ideal for these complex features. Progress also continues on EUV mask development, which will require extreme mask writing precision as well as high shape counts. However, with all of these major technology transitions, the computational power required to precisely simulate the physical effects of photomask designs and semiconductor processes will skyrocket—driving the need for GPU acceleration to enable simulation-based processing in reasonable run times.”

The first two units of the fifth-generation CDP will be delivered by the end of the second calendar quarter of 2017. D2S will present a paper co-authored with NuFlare Technology on GPU-accelerated inline linearity correction during the “Use of GPU in Mask Making II” session at the Photomask Japan 2017 Symposium. A white paper on the benefits of GPU acceleration is available for download here.

Packaging and test
Advanced Semiconductor Engineering (ASE) announced that its Singapore IC testing and backend wafer-level chip scale packaging facility has received the Common Criteria certification. Common Criteria is a framework that outlines the requirements for globally recognized standards and security inspections for IT products. It is designed for products and applications that are targeted for high security-intensive markets, such as the government, banking or defense sectors. ASE Singapore is certified at Evaluation Assurance Level 6, the second highest level of stringency.

ATTOPSEMI Technology has joined GlobalFoundries’ FDXcelerator Partner Program, to provide a scalable, non-volatile one-time programmable (OTP) memory IP to be compatible with GF’s 22FDX technology.

Market research
Apple’s move to adopt TSMC’s fan-out packaging technology for its A10 applications processor has changed the packaging landscape. It has also impacted the related equipment and materials markets. The total fan-out WLP equipment market is expected to reach about $694 million in 2021, a CAGR of 42.5% between 2015 and 2021, according to Yole Développement. Similarly, fan-out’s total materials market is expected to reach about $148 million in 2021 at a CAGR of 40% during the same period, according to the research firm.

The global semiconductor materials market increased 2.4% in 2016 compared to 2015 while worldwide semiconductor revenues increased 1.1%, according to SEMI. Total wafer fabrication materials and packaging materials were $24.7 billion and $19.6 billion, respectively, according to SEMI.

Related Stories
Manufacturing Research Bits: April 4
Open-source tomography; 4D metrology; new mass spectrometry.
China: Fab Boom or Bust?
A frenzy of activity is causing lots of speculation about how this complex market will evolve.
The Week In Review: Manufacturing; March 31
New node metrics; DDR5 standard; fab tool service awards; IC forecasts.

Leave a Reply

(Note: This name will be displayed publicly)