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Layout Driven Design With L-Edit Photonics
By Mentor, a Siemens Business - 31 Oct, 2018 - Comments: 0

Advances in integrated circuit technology and fabrication have made it possible to leverage traditional CMOS fabrication processes and materials and apply them to the design of Photonic Integrated Circuits (PICs). The combination of PICs with traditional electronic integrated circuits, called integrated photonics, is the ability to move, modulate, and detect light on a single IC. While there is... » read more

System-Level, Post-Layout Electrical Analysis For High-Density Advanced Packaging
By Mentor, a Siemens Business - 24 Oct, 2018 - Comments: 0

As HDAP designs become more popular, the need for post-layout simulation (analog) and post-layout STA (digital) flows to augment basic physical verification (DRC and LVS) is growing. Mentor provides an accurate, automated flow that generates the required HDAP netlist for simulation/STA to enable HDAP designers to ensure that the HDAP will perform as designed. To read more, click here. » read more

Boosting Regression Throughput By Reusing Setup Phase Simulation
By Mentor, a Siemens Business - 10 Oct, 2018 - Comments: 0

This paper discusses how to write a design so the common initial setup phase simulation is done once and then used as a foundation to run different tests later on, including the ability to change test stimulus to simulate different test behaviors. It also discusses what type of designs are appropriate for this methodology and what a designer can do to make his/her design suitable for it. Also c... » read more

Improving In-System Test With Tessent VersaPoint Test Point Technology
By Mentor, a Siemens Business - 08 Oct, 2018 - Comments: 0

This paper describes a new versatile test point technology called VersaPoint, which has been developed specifically to work with designs implementing mixed EDT/LBIST methodologies to reduce EDT pattern counts and improve Logic BIST (LBIST) test coverage. VersaPoint test points can reduce compressed pattern counts 2X to 4X beyond compression alone and improve LBIST test coverage beyond what is p... » read more

Proof-Of-Concept To Product: Initial Design Of A MEMS Sensor
By Mentor, a Siemens Business - 03 Oct, 2018 - Comments: 0

In previous papers, we have covered how to design and verify an IoT tank fluid-level monitoring system. We covered how to create a proof-of-concept and prototype. In this series of white papers, we explore the detailed product design of the MEMS pressure sensor within this system. In this initial whitepaper, we introduce the piezoelectric micro-machined ultrasonic transducer (PMUT) sensor, show... » read more

Using CAA And DFM Scoring To Improve Manufacturing Success
By Mentor, a Siemens Business - 26 Sep, 2018 - Comments: 0

Critical area analysis and design for manufacturing scoring both offer designers actionable information they can use to improve their designs to prevent low-yield issues in the foundry. At the same time, they provide the foundry with information they can use for process improvement. Learn how fabless designers, foundries, and integrated device manufacturers can all benefit from addressing manuf... » read more

Low Power Coverage: The Missing Piece In Dynamic Simulation
By Mentor, a Siemens Business - 12 Sep, 2018 - Comments: 0

Through real design examples and case studies, this paper demonstrates how to achieve comprehensive low power design verification closure with all possible sources of power states, their transition coverage, and cross-coverage of power domains of interdependent states. As well the paper proposes a mechanism to combine and represent LP and non-LP coverage in a unified and adaptable database with... » read more

Tessent Cell-Aware Test
By Mentor, a Siemens Business - 10 Sep, 2018 - Comments: 0

Tessent Cell-Aware ATPG is a transistor-level ATPG-based test methodology that achieves significant quality and efficiency improvements by directly targeting specific shorts; opens and transistor defects internal to each standard cell; resulting in significant reductions in defect (DPM) levels. Traditional scan patterns are created using fault models that are based on the logical operation of t... » read more

‘Fuzzing’ A Virtual Prototype ECU To Improve Security
By Mentor, a Siemens Business - 05 Sep, 2018 - Comments: 0

Staying ahead in the arms race against hackers means constantly looking for novel ways to find and correct security flaws, including (and perhaps especially) when it comes to relatively low-level hardware. In this brief white paper we describe one such way — an automated fuzzing test of a virtual ECU to find and correct vulnerabilities during the upstream development process. To read more,... » read more

Accelerating Test Pattern Bring-Up For Rapid First Silicon Debug
By Mentor, a Siemens Business - 22 Aug, 2018 - Comments: 0

Reducing the time spent on silicon bring-up is critical in getting ICs into the hands of customers and staying competitive. Typically, the silicon bring-up process involves converting the test patterns to a tester-specific format and generating a test program that is executed by Automatic Test Equipment (ATE). This standard silicon bring-up flow is becoming too slow and expensive, especially fo... » read more

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