Author's Latest Posts

Efficient Sensitivity-Aware Assessment Of High-Speed Links Using PCE And Implications For COM
By Mentor, a Siemens Business - 09 Sep, 2020 - Comments: 0

This technical white paper, originally presented at DesignCon, investigates the challenges of increased data rates and reduced margins in high-speed link design. Section 1: Introduction Section 2: State of the Art Link Evaluation and Assessment of Parameter Variability Section 3: Proposed Modeling Framework Section 4: Sensitivity Analysis of a High-Speed Interconnect Section 5: Conclusio... » read more

Critical Area-Based Test Pattern Optimization For High-Quality Test
By Mentor, a Siemens Business - 02 Sep, 2020 - Comments: 0

Among the challenges for DFT engineers is how to set a target metric for ATPG and how to choose the best set of patterns. Traditional coverage targets based on the number of faults detected doesn’t consider the likelihood of one fault occurring compared to another. Tessent developed total critical area ATPG technology that enables the sorting and ordering of patterns based on their likelihood... » read more

Accelerate Time To Market With Calibre nmLVS-Recon Technology
By Mentor, a Siemens Business - 27 Aug, 2020 - Comments: 0

One thing is clear…tapeouts are getting harder, and taking longer. As part of a growing suite of innovative early-stage design verification technologies, the Calibre nmLVS-Recon tool enables design teams to rapidly examine dirty and immature designs to find and fix high-impact circuit errors earlier and faster, leading to an overall reduction in tapeout schedules and time to market. To rea... » read more

PCIe Simulation Speed-Up Using Mentor QVIP With PLDA PCIe Controller For DMA Applications
By Mentor, a Siemens Business - 12 Aug, 2020 - Comments: 0

In this case study, PLDA explains how verification engineers can use Mentor’s Questa Verification IP (QVIP) to improve productivity during the functional verification of PCIe designs with DMA engines. The flexibility of Questa VIP was key to creating custom testbenches from scratch that can dynamically adapt to different IP topologies and configurations, mixing PCIe interfaces with multiple A... » read more

Re-Imagining Electrical System Design
By Mentor, a Siemens Business - 05 Aug, 2020 - Comments: 0

Electrical system complexity is reaching a tipping point across industries, from modern passenger vehicles to sophisticated industrial machines that can now contain nearly 5,000 wiring harnesses. The electrical systems of these machines contain multiple networks, thousands of sensors and actuators, miles of wiring and tens of thousands of discrete components. Designing these complex systems is ... » read more

Multi-Mode Clock Domain Crossing Verification Enables Analysis Efficiency And Accuracy
By Mentor, a Siemens Business - 29 Jul, 2020 - Comments: 0

This paper shows how automated modal CDC analysis is used to exhaustively verify CDC issues in all test and operational modes of an SoC with multiple IPs. This new approach automatically consolidates all results from each mode, making issues very easy to interpret and debug. What took days and weeks with the prior manual approach now takes only a few hours. To read more, click here. » read more

Fast And Accurate Variation-Aware Mixed-Signal Verification Of Time-Domain 2-Step ADC
By Mentor, a Siemens Business - 08 Jul, 2020 - Comments: 0

To meet today’s analog-to-digital converter (ADC) specifications and to produce a high-yield design, teams typically need to perform extensive brute force mixed-signal simulations to account for all potential design variation. However, at nanometer nodes, the number of process, voltage and temperature (PVT) corners and parametric variation grow exponentially making the simulation impractical ... » read more

Using Built-In Self-Test Hardware To Satisfy ISO 26262 Safety Requirements
By Mentor, a Siemens Business - 30 Jun, 2020 - Comments: 0

The promise of autonomous vehicles is driving profound changes in the design and testing of automotive semiconductor parts. The ICs for safety-critical applications need to meet the ISO 26262 standard for functional safety. Among the challenges in the design flow has been aligning the metrics for design-for-test and for functional safety. This paper describes using logic built-in-self-test as b... » read more

EDA In The Cloud — Why Now?
By Mentor, a Siemens Business - 24 Jun, 2020 - Comments: 0

What is the value of cloud computing to my company? Learn how the cloud became a viable option for IC verification, and explore the ways your company can best use cloud resources to expand your compute options for both established nodes and leading-edge technologies. To read more, click here. » read more

Using Calibre For Advanced IC Packaging Verification And Signoff
By Mentor, a Siemens Business - 10 Jun, 2020 - Comments: 0

As high density advanced package designs evolve and become more common, an automated LVS-like flow to detect and highlight package connectivity errors is required. We explain the most common package verification issues and how designers can resolve them using using Xpedition Substrate Integrator and Calibre 3DSTACK to provide a significant advantage over traditional LVS flows for HDAP. To re... » read more

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