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Developing Effective Design Strategies For Today’s Wearable Devices: Power Management


As the next wave of wearable devices expands into a new class of revolutionary and innovative products, there will be a growing importance placed on the real-time operating system (RTOS) and corresponding middleware. Wearable System-on-Chip (SoC) processors require an operating system optimized for size and performance with power-efficient wireless connectivity options needed for machine-to-mac... » read more

Securing Modern-day Devices With Embedded Virtualization And ARM TrustZone Technology


When securing today’s modern devices, it’s not enough to know the type of device you want to secure. Equally important is the process used to develop that device. In this paper, we’ll take a closer look at security as it relates to protecting data, building security into a device, and securing SoCs in multicore architectures. ARM TrustZone technology, which provides a solution for carving... » read more

Developing Effective Design Strategies for Today’s Wearable Devices: Power Management


As the next wave of wearable devices expands into a new class of revolutionary and innovative products, there will be a growing importance placed on the real-time operating system (RTOS) and corresponding middleware. Wearable System-on-Chip (SoC) processors require an operating system optimized for size and performance with power-efficient wireless connectivity options needed for machine-to-mac... » read more

When Order Matters


Debugging DP errors can be not only time-consuming, but also frustrating, when new errors seem to appear out of nowhere. The order in which you address DP errors can make a significant difference in the efficiency of your debug efforts. Learning the sequence of ordered DP debugging explained in this white paper can not only help you reduce the time you spend analyzing and fixing DP errors, but ... » read more

Power Aware CDC Verification Of Dynamic Frequency And Voltage Scaling (DVFS) Artifacts


Traditional low power verification only validates the functional correctness of power control logic, but it does not validate the impact of power logic on multi-clock logic. We will discuss the effects of advanced low power design on CDC design and verification. This paper describes the new CDC issues caused by the addition of power control logic including isolation cells, retention cells, lev... » read more

Addressing The Challenges Of IoT Design


Internet of Things (IoT) designs mesh together several design domains in order to successfully develop a product. Individually, these design domains are challenging. Bringing them all together to create an IoT product can place extreme pressure on design teams. The Tanner design flow is architected to seamlessly work in any of these design domains by employing an integrated design flow for desi... » read more

6 Key Benefits Of Thermal Testing


This whitepaper discusses the advantages of transient thermal test methods for IC package and thermal interface material (TIM) thermal characterization testing vs steady state methods. These methods assist verification of thermal performance for reliability, support package development & manufacturing decision making, and ensure accurate data sheet values used for selection by engineers. ... » read more

Enhancing Automotive Electronics Reliability Checking


While complexity in the automotive electronics space continues to increase, ensuring reliability in safety-critical systems is crucial to the success and reputation of the automotive industry. Automation of complex reliability verification tasks provides a robust and repeatable mechanism for building reliable automotive IC designs within market-driven schedules. Utilizing advanced reliability v... » read more

SoC Verification For The Internet of Things


Larger, more complex designs with more software and tighter power budgets require new verification solutions that target the associated technological challenges. This paper explores why traditional digital simulation and hardware prototypes fall short when it comes to verifying IoT and network designs, why using emulation is critical for a total verification solution, and why traditional in-cir... » read more

10 Common Device Noise Analysis Mistakes


Device noise is critical in nanometer-scale CMOS processes, and it fundamentally limits the performance of many circuits at 45 nm and below. Given the right tools, device noise analysis (DNA) is a fairly straightforward process that should produce results that are within 1 dB to 2 dB of silicon measurements. However, there are a number of common mistakes that can lead to grossly overestimating ... » read more

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