Michael Hargrove

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Michael Hargrove is a a semiconductor process and integration engineer at Coventor, a Lam Research Company. He has worked in the semiconductor technology development business for more than 30 years. He began his career at IBM, where he worked on advanced CMOS technology development. He then spent five years at Epson Research and Development, working on high-speed/high-frequency device design and characterization. He later joined AMD, where he worked on high-k/metal gate technology. Hargrove subsequently transitioned to GlobalFoundries Research and Development in Albany, NY. At Coventor his focus is 3D semiconductor process modeling. Hargrove received his Ph.D. from the Thayer School of Engineering at Dartmouth College, in Hanover, N.H.

Author's Latest Posts

Quantum Computers And CMOS Semiconductors: A Review And Future Predictions
By Michael Hargrove - 16 Jun, 2022 - Comments: 0

With the advent of quantum computing, the need for peripheral fault-tolerant logic control circuitry has reached new heights. In classical computation, the unit of information is a “1” or “0”. In quantum computers, the unit of information is a qubit which can be characterized as a “0”, “1”, or a superposition of both values (known as a “superimposed state”). The control c... » read more

Advancing To The 3nm Node And Beyond: Technology, Challenges And Solutions
By Michael Hargrove - 19 Aug, 2021 - Comments: 0

It seems like yesterday that finFETs were the answer to device scaling limitations imposed by shrinking gate lengths and required electrostatics. The introduction of finFETs began at the 22nm node and has continued through the 7nm node. Beyond 7nm, it looks like nanosheet device structures will be used for at least the 5nm and probably the 3nm nodes. The nanosheet device structure is the brainc... » read more

Semiconductor Memory Evolution And Current Challenges
By Michael Hargrove - 16 Jul, 2020 - Comments: 0

The very first all-electronic memory was the Williams-Kilburn tube, developed in 1947 at Manchester University. It used a cathode ray tube to store bits as dots on the screen’s surface. The evolution of computer memory since that time has included numerous magnetic memory systems, such as magnetic drum memory, magnetic core memory, magnetic tape drive, and magnetic bubble memory. Since the 19... » read more

Connecting Wafer-Level Parasitic Extraction And Netlisting
By Michael Hargrove - 18 Apr, 2019 - Comments: 0

The semiconductor technology simulation world is typically divided into device-level TCAD (technology CAD) and circuit-level compact modeling. Larger EDA companies provide high-level design simulation tools that perform LVS (layout vs. schematic), DRC (design rule checking), and many other software solutions that facilitate the entire design process at the most advanced technology nodes. In thi... » read more

A Review of Silicon Photonics
By Michael Hargrove - 20 Aug, 2018 - Comments: 0

With the end of Moore’s Law rapidly approaching—some say it's already here—new applications of older technologies are gaining attention. One specific area of interest is photonics. The National Center for Optics and Photonic Education defines photonics as the technology of generating and harnessing light and other forms of radiant energy whose quantum unit is the photon. It can also be... » read more

Transistor-Level Performance Evaluation Based On Wafer-Level Process Modeling
By Michael Hargrove - 30 May, 2018 - Comments: 0

Three years ago, I wrote a blog entitled “Linking Virtual Wafer Fabrication Modeling with Device-level TCAD Simulation,” in which I described the seamless connection between the SEMulator3D virtual wafer fabrication software platform and external third-party TCAD software. I’m now happy to report that device-level I-V performance analysis is now a built-in module within the SEMulator3D so... » read more

The Advantages Of FD-SOI Technology
By Michael Hargrove - 18 Jan, 2018 - Comments: 0

If my memory serves me well, it was at the 1989 Device Research Conference where the potential merits of SOI (Silicon on Insulator) technology were discussed in a heated evening panel discussion. At that panel discussion, there were many advocates for SOI, as well as many naysayers. I didn’t really think more about SOI technology until the mid-nineties, when I was sitting in a meeting where t... » read more

Reducing BEOL Parasitic Capacitance Using Air Gaps
By Michael Hargrove - 19 Oct, 2017 - Comments: 0

Reducing back-end-of-line (BEOL) interconnect parasitic capacitance remains a focus for advanced technology node development. Porous low-k dielectric materials have been used to achieve reduced capacitance, however, these materials remain fragile and prone to reliability concerns. More recently, air gap has been successfully incorporated into 14nm technology [1], and numerous schemes have been ... » read more

What Drives SADP BEOL Variability?
By Michael Hargrove - 18 May, 2017 - Comments: 0

Until EUV lithography becomes a reality, multiple patterning technologies such as triple litho-etch (LELELE), self-aligned double patterning (SADP), and self-aligned quadruple patterning (SAQP) are being used to meet the stringent patterning demands of advanced back-end-of-line (BEOL) technologies. For the 7nm technology node, patterning requirements include a metal pitch of 40nm or less. This ... » read more

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