Author's Latest Posts


Die-to-Die Interconnects for Chip Disaggregation


Today, data growth is at an unprecedented pace. We’re now looking at petabytes of data moving into zettabytes. What that translates to is the need for considerably more compute power and much more bandwidth to process all that data. In networking, high-speed SerDes PHYs represent the linchpin for blazing fast back and forth transmission of data in data centers. In turn, demand is increa... » read more

Die-To-Die Interconnects For Chip Disaggregation


Today, data growth is at an unprecedented pace. We’re now looking at petabytes of data moving into zettabytes. What that translates to is the need for considerably more compute power and much more bandwidth to process all that data. In networking, high-speed SerDes PHYs represent the linchpin for blazing fast back and forth transmission of data in data centers. In turn, demand is increasin... » read more

ADAS Further Extends 7nm Challenges


As we discussed previously on the LPHP blog, 7nm nodes hold great promise for reducing power, improving performance and increasing density for next-generation chips, but also present a set of engineering challenges. When you factor in the standards set for autonomous vehicles (AV) and advanced driver assistance systems (ADAS) system-on-chips or SoCs, those challenges can more than double. Autom... » read more

5G Wireless Infrastructure Pushes High-Speed SerDes Protocols


5G is the 5th generation wireless system standard that, through high speeds and increased accessibility, promises to change the way we stream, communicate, work, and travel. Boasting speed capabilities of 20Gbps and network densities of 1 million connected devices per square kilometer, 5G is the required technology for the implementation of highly anticipated technologies like autonomous vehicl... » read more