PCIe 4.0 Hangs In, PCIe 5.0 Coming On Strong

While PCIe 5.0 offers higher performance and lower latency, Gen 4 is likely stay dominant in many markets.


First introduced in 2003 as a universal serial chip-to-chip interface running at 2.5 Gbps, PCI Express (Peripheral Component Interconnect Express), also known as PCIe, has advanced several revisions with significant improvements to performance and other features with each new generation.

Through broad support, backwards compatibility, and a consistent cadence of upgrades that doubled lane speeds every 3-4 years, PCIe has been solidified as the go-to high-speed SerDes standard for many applications from consumer to High Performance Computing (HPC). Despite the 7-year gap between the release of PCIe 3.0 and PCIe 4.0, there is strong expectation that the cadence between generations will be significantly accelerated as we move to PCIe 5.0. With new revisions of the specification expected to come out later this year, the shortened time between generations will create an overlap in availability, forcing chip designers to make case-by-case decisions between Gen 4 and Gen 5 based on their application-specific needs.

With support for data rates of 16 gigabits per second (Gbps), PCIe Gen 4 is fast becoming the de facto standard throughout many major markets including data center, high-performance computing (HPC), communications, automotive and consumer. But with PCIe Gen 5 fast approaching, many of the more performance-intensive applications, such as data center, networking and HPC, will begin to quickly transition to the latest generation.

The growing demand for data in these applications has been the driving factor for increased interface speeds throughout the data center. Today, most interfaces between processor to switch, processor to storage, and processor to processor in high-performance applications are moving to data rates of 25 Gbps and beyond. With the industry moving toward Terabit Ethernet standards like 200GbE and 400GbE, server link speeds are progressing to 56 and 112Gbps. To keep pace with these growing bandwidth requirements, PCIe 5.0 will support data rates of 32 Gbps while improving other key features as well.

There are additional improvements beyond pure performance expected in PCIe 5.0 that will spur early adoption in high-bandwidth applications. Server applications are very sensitive to latency and typically send data through multiple connectors and extensive cabling with channel losses of 25 dB and beyond. Therefore, ASICs used for these applications require PHYs with leading receiver sensitivity, bit error rates (BER) at less than 1E-15, and eye height/width margins.

To address these requirements, PCIe 5.0 is overhauling the PIPE interface to reduce pin count and latency and introducing support for an increased channel loss of up to 36 dB to serve long-reach requirements. As a result, next-generation server CPUs are expected to be the first drivers for adoption and will trigger the ramp up of PCIe 5.0 in the industry starting in 2020.

However, the launch of PCIe 5.0 doesn’t mean the end for PCIe 4.0. Despite the overlap in production between Gen 4 and Gen 5, many applications won’t need the bump in performance any time soon. For example, consumer and automotive markets don’t need 32 Gbps data rate. These applications are well served by the 16 Gbps delivered by PCIe 4.0 and don’t require the reduced latency or increased support for channel loss promised by the next generation. For this reason, PCIe 4.0 is expected to have a sustained long life even after PCIe 5.0 goes into production for high-performance applications.

Faced with the choice between PCIe 4.0 and 5.0, chip designers will need to weigh their options based on the needs of their applications with those demanding the highest performance being the first to migrate to Gen 5. With PCIe 4.0 reaching volume production this year and production of PCIe 5.0 likely just a few years behind, PCIe will remain the standard of choice in a broad range of applications with Gen 4 and Gen 5 having a sustained period of coexistence in the market.

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