Author's Latest Posts

Introduction To Voltage Droop And Mitigation

By Movellus - 10 Feb, 2025 - Comments: 0

Voltage droop continues to plague high-performance SoCs, and not all mitigation systems are designed equal. When you have a choice, its always better to measure and quantify the differences. This paper provides a system-level introduction to voltage droop, along with a framework for measuring potential Vmin savings, and a way to answer the age-old question, "Is my mitigation system fast enough?... » read more

Integrated, Turnkey Droop Response System: Heterogeneous IP Use Case

By Movellus - 29 May, 2024 - Comments: 0

Whether you serve the ADAS, PC, or networking market, chances are that your SoC is heterogeneous; containing general processors and application-specific accelerators. Your solution might have a systolic array for convolutions, a cluster of CPUs for application code, or a look-aside crypto engine for packet security. While application-specific accelerators significantly improve performance and p... » read more

Aeonic Generate GGM High Performance SoC Clock Generation Module

By Movellus - 24 Apr, 2024 - Comments: 0

Core counts have been increasing steadily since IBM's debut of the Power 4 in 2001, eclipsing 100 CPU cores and over 1,000 for AI accelerators. While sea of processor architectures feature a stamp and repeat design, per-core workloads aren't always going to be symmetrically balanced. For example, a cloud provider (AI or compute) will rent out individual core clusters to customers for specialize... » read more

Sea Of Processors Use Case

By Movellus - 27 Mar, 2024 - Comments: 0

Remote Droop Detection And Response Use Case

By Movellus - 28 Feb, 2024 - Comments: 0

While sea of processor architectures feature a stamp and repeat design, per-core workloads aren't always symmetrically balanced. For example, a cloud provider (AI or compute) will rent out individual core clusters to customers for specialized and varied workloads. However, this asymmetry, combined with rapid provisioning changes, can lead to global voltage droops on the SoC resulting in potenti... » read more

Synchronous Die-to-Die Signaling Using Aeonic Connect

By Movellus - 26 Jul, 2023 - Comments: 0

This paper presents a system providing accurate clock alignment for on-die and die-to-die synchronous circuits. A low-frequency reference clock provides an accurate timing reference with low power consumption, while distributed delay lines align the endpoints of loosely constrained clock trees. For on-die clocks, this synchronization strategy severs the traditional relationship between power an... » read more