Simplify DFT For Advanced SoCs

By Ron Press - 08 Feb, 2022 - Comments: 0

The purpose of electronic design automation (EDA) software is to solve SoC design problems and simplify the entire process. For design for test (DFT), this means aiming to streamline the DFT development for today’s large and complex designs. The technologies and methods developed through partnerships between EDA suppliers, foundries, and semiconductor companies should effectively reduce risk,... » read more

Using Critical Area To Boost Automotive IC Test Quality

By Ron Press - 03 Sep, 2020 - Comments: 0

To compete in the fast-growing market for automotive ICs, semiconductor companies need to address new challenges across the entire design flow. To meet the ISO 26262 goal of zero defective parts per million (DPPM), DFT engineers have embraced new test pattern types, including cell-aware, interconnect, and inter-cell bridge (cell neighborhood). But the traditional methods of choosing the types o... » read more

Smart Plug-And-Play DFT For Arm Cores

By Ron Press - 11 Jun, 2019 - Comments: 0

Modern SoCs are experiencing continued growth in capabilities and design sizes with more and more subsystem IPs being implemented. These large, complex, multi-core SoCs need strategies for DFT and ATPG that effectively reduce DFT effort, minimize ATPG runtime, and still achieve the target test coverage. Hierarchical DFT enables designing and testing of these designs in a systematic and repeatab... » read more

Smarter DFT Infrastructure And Automation Emerge As Keys To Managing DFT Design Scaling

By Ron Press - 21 Dec, 2017 - Comments: 0

By Ron Press and Vidya Neerkundar The reality of DFT for large and complex SoCs has introduced new risk into design schedules. DFT teams end up in the critical path to tape out while waiting for portions of the design to be complete, and there are more DFT integration steps than ever before. The traditional approaches to DFT work on huge designs pose problems of repeatability and reliability... » read more