Using Critical Area To Boost Automotive IC Test Quality

Driving automotive ICs to zero DPPM by taking the likelihood of defects into account.


To compete in the fast-growing market for automotive ICs, semiconductor companies need to address new challenges across the entire design flow. To meet the ISO 26262 goal of zero defective parts per million (DPPM), DFT engineers have embraced new test pattern types, including cell-aware, interconnect, and inter-cell bridge (cell neighborhood). But the traditional methods of choosing the types of patterns to apply and setting coverage targets is leaving improvements to quality, test time, and test cost on the table.

Test coverage targets for static and dynamic patterns targeting stuck-at and transition fault models, respectively, are usually based on the percent of faults detected. These targets vary by company and it often takes years of production fail data to decide on appropriate goals. When a company needs to add a new fault model, the target could be completely different than test coverage based on the full fault list. For example, consider targeting a test coverage for all potential bridge faults—this could be a huge list. You might achieve 99% detection of all bridge faults but miss hundreds of the most likely bridges. To reduce DPPM, it is more effective to choose the subset of bridges that is most likely to occur.

However, the state-of-the-art way is to choose patterns by test coverage by dividing detected number of faults or defects by the total number of faults or defects. Such a calculated test coverage has no relation to the probability of occurrences of manufacturing defects for individual faults, making it unrealistic to create an optimal pattern set. This leads to overly-large test pattern sets, longer than necessary test time, and lower confidence in estimates of IC quality. These are realistic and common issues faced today that are of particular concern for meeting the DPPM requirements of automotive ICs.

Critical area as a metric for test

The new approach to this challenge, developed in close partnerships with industry-leading semiconductor companies, measures pattern value assessment based on the likelihood of the physical defects occurring. You calculate the total critical area (TCA) associated with faults detected by a pattern. In other words, we first determine the likelihood of defects occurring based on their critical area, then we can sort the various pattern sets considering the defects they detect to choose the most effective patterns to apply.

TCA provides a common metric to assess a pattern’s impact on DPM, which can be used to sort or order patterns to achieve the lowest DPPM. Using TCA, you can mix in patterns targeting new fault models for a more effective pattern set, even with the same number of patterns as your original pattern set. You can select or sort the most effective patterns from your entire pattern set based on their ability to detect physical defects.

Critical area is the area in a design layout that determines the likelihood that a specific physical defect can cause a failure in the design (figure 1). TCA is the sum of all individual critical areas of a short between two connectors, or an open in a connection, weighted by the probability of occurrence of that spot size. Instead of just counting faults, TCA coverage takes the likelihood of defects into account and provides a consistent metric for all fault models.

Fig. 1: Total critical area calculations for a bridge between two nets.

TCA values are calculated using physical layout information. A user-defined fault model (UDFM) file stores the models for each defect type (cell-internal, bridge, open, cell-neighborhood). Anyone using cell-aware or automotive-grade ATPG will be familiar with UDFM files. The UDFM files are input to the ATPG tool to generate test patterns and can be used to perform layout aware and cell-aware failure diagnosis. When read into the ATPG tool, the UDFM files containing TCA fault data can be applied to patterns to sort them from highest TCA to lowest.

Features of using TCA include:

  • Selecting the most effective patterns
  • Choosing targets for pattern types and coverage
  • Determining the effectiveness of new pattern types
  • Grading pattern value by likelihood to detect defects
  • Automatically sorting and selecting patterns
  • Creating a smaller pattern set by targeting multiple fault models in our ATPG run

This is the first time that total critical area calculation for all defects in the digital logic part of a chip has been available in a commercial ATPG tool. Using TCA to built the most effective and efficient test patterns for your automotive IC ensures that the device meets the ISO 26262 quality guidelines and is competitive in the market.

Read more in the whitepaper Critical area based pattern optimization for high-quality test.

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