Smarter DFT Infrastructure And Automation Emerge As Keys To Managing DFT Design Scaling

Ensure a high rate of success at each step in the DFT flow by adopting a smarter methodology.

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By Ron Press and Vidya Neerkundar

The reality of DFT for large and complex SoCs has introduced new risk into design schedules. DFT teams end up in the critical path to tape out while waiting for portions of the design to be complete, and there are more DFT integration steps than ever before. The traditional approaches to DFT work on huge designs pose problems of repeatability and reliability. With more DFT steps, the overall rate of success declines unless the rate of success at each step is extremely high. So, how do you ensure an extremely high rate of success at each step in the DFT flow? By adopting a smarter DFT methodology that includes:

  • Plug-and-play infrastructure to connect and manage the inserted DFT logic, and to manage other design components during test.
  • Automation to improve the reliability of your DFT flows. Any manual steps add risk to the DFT methodology.
  • Customization to facilitate company- specific flows or operations.

The best and most widely adopted DFT methodologies involve plug-and-play structural approaches. These approaches take very big complex logic and functionality and divide them into dramatically simpler parts that can be managed and tested with automation. This hierarchical DFT removes the effort of pattern generation on the full design and enables concurrent test insertion on multiple blocks. Test patterns generated for a block do not need to be regenerated during chip-level pattern generation; they can be directly reused or “retargeted.” This ability to retarget block-level patterns through multiple levels of hierarchy is itself a good enough reason for many designs to use hierarchical flows. After all, when the patterns do not need to be regenerated, you save not just time and resources, but you also improve reliability, which in turn increases success.

Hierarchical DFT is aided by an IJTAG IEEE 1687 infrastructure, which simplifies the integration, configuration, and test initialization of all on-chip blocks, including third-party IP. Without IJTAG, the access to the devices connected must be specified on a per-cycle basis and, in the majority of cases, the path that needs to be accessed also needs to be configured and specified by the user. This manual process of figuring out the path by which the specific controller needs to be accessed is both time-consuming and error-prone. Eliminating this manual step is how the plug-and-play infrastructure improves not just automation but also reliability.

In addition to a plug-and-play DFT methodology, further automating as many DFT steps as possible also reduces risk and improves the efficiency and reliability of the entire design flow. Look for DFT tools that share a common tool environment and database. What types of tasks should be highly automated?

  • Memory and logic BIST scannability; all your DFT tools should share data on how to configure the BIST logic for use during scan configuration and test.
  • Boundary scan logic reuse; should be automatically configured to be efficiently utilized during scan test.
  • Pattern retargeting automation; block-level pattern retargeting should automatically adjust when it recognizes inversions, pipelines, and more in the top-level embedding. It should also automatically retarget block-level DRCs to ensure the block-level patterns can be appropriately applied at the top level.
  • IJTAG setup porting; if the DFT infrastructure is implemented with IJTAG, block-level pattern setup is automatically embedded in the top-level setup.

As an example of automation during pattern generation at the top level where cores are in external mode, see Figure 1. All information from the block level that needs to be transferred to the next level is retargeted automatically.


Figure 1. Example of automation that helps with top-level pattern generation.

The DFT tool understands all of the initialization setup for the blocks and all of the DFT logic present in the block, like On-chip Clock Controllers, BIST logic, or compression logic. It automatically performs any procedures that need to be mapped from a block to the next level. Automatic learning and configuration of IJTAG network and setup is easily performed, which otherwise may require 100s of manual operations. The same also applies for BIST and scan patterns. With extensive automation, the manual steps for pattern generation and pattern retargeting is tremendously reduced, which helps in achieving a high rate of DFT success.

Finally, customization in your DFT flow is important. Particularly with hierarchical DFT flows, there are usually design-specific tasks that need to be customized across the blocks. The DFT tools need to have a scripting environment that makes these batch operations easy and reliable.

For example, say you want to find all clock gater modules below an instance “core_a” and edit the connections to add an AND gate and disable signal. You should be able to do this with just a few lines of code, as shown in Figure 2.


Figure 2. Example of a script to provide reliable and repeatable edits across many instances in the design.

Designs continue to scale and add new challenges to design and test teams. Smarter DFT methodologies and powerful, flexible automation boost the overall DFT success rate by reducing risk and ensuring reliability and predictability in DFT flows. Hierarchical DFT enables concurrent DFT development and integration, similar to how other design development work is done. Automation is used to connect and manage the DFT infrastructure to dramatically reduce the risk so that the many required process steps can run successfully. Customization makes design-specific tasks easy and boosts the efficiency of the entire flow. With a smarter DFT infrastructure, DFT teams will no longer find themselves in the critical path to tape out.

Vidya Neerkundar is a technical marketing engineer at Mentor, a Siemens business.



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