ASIC/IC Trends With A Focus On Factors Of Silicon Success


“The more you know, the more you know you don't know.” ― Aristotle, 4th C. BC When Aristotle uttered this humble aphorism, he wasn’t telling us to throw up our hands and not bother with learning. He was encouraging us to continue digging deeper, to get answers and ask questions of those answers — that the thrills and rewards of study are truly without end. This is a big part of ou... » read more

Trends In FPGA Verification Effort And Adoption: The 2018 Wilson Research Group Functional Verification Study


As contributors and pioneers in the digital revolution, we are often so busy creating and innovating that we are compelled to focus on the trees, never mind the forest. But as we are all aware, the more we know about the bigger picture, context, historical and projected trends, or simply how other people are doing the same thing, the more efficiently and successfully we can do our jobs. Prov... » read more

Methodologies And Flows In A Rapidly Changing Market


A growing push toward more heterogeneity and customization in chip design is creating havoc across the global supply chain, which until a couple years ago was highly organized and extremely predictable. While existing tools still work well enough, no one has yet figured out the most efficient way to use them in a variety of new applications. Technology is still being developed in those marke... » read more

Re-using Common Simulation Set-Up Processes To Speed Regression


Functional verification of SoCs always has some kind of set up process. For complex SoCs, at least, this initial set up phase often consumes from 20 to 90% of each test’s total simulation time. And thousands of tests are run in the verification of a design. This set up phase could be either executing the exact same sequence of simulation steps, or programming the design to reach the same i... » read more

Overcoming Low Power Verification Challenges For Mixed-Signal SoC Designs


With increasing SoC complexity and advanced power-aware architectures, a robust low power verification methodology is important for signing off the design at different stages from RTL through netlist. For mixed-signal SoCs, the challenge is, there is no well-defined low power methodology, nor are the industry’s low power verification tools equipped to handle custom designs. This article propo... » read more

The Coming Golden Age For Automotive E/E Design Services And Consulting


By Andrew Macleod and Scott Majdecki The discipline of automotive E/E systems design is being transformed by trends like electrification and autonomous vehicles, which means there is a premium on methodologies like rapid platform (hardware/ software) prototyping, simulation and test, and electrical architecture optimization. Such methodologies hinge on advanced software design tools and the ... » read more

By the Power Vested in Me, I Now Pronounce You (The SoC Designer)…


…Doomed. Well, maybe that’s a little harsh, but your job won’t be getting any easier; that “happily ever after” may be harder to achieve than you think, and there are a number of reasons why. And by “me” (of vested power), here I’m really talking about the power of the consumer market as a whole and our collective insatiable demand for newer, shinier…well, just plain “coo... » read more

Smarter DFT Infrastructure And Automation Emerge As Keys To Managing DFT Design Scaling


By Ron Press and Vidya Neerkundar The reality of DFT for large and complex SoCs has introduced new risk into design schedules. DFT teams end up in the critical path to tape out while waiting for portions of the design to be complete, and there are more DFT integration steps than ever before. The traditional approaches to DFT work on huge designs pose problems of repeatability and reliability... » read more

Addressing Power Integrity Challenges For SoCs


Power integrity has become a crucial part of the system-on-a-chip (SoC) design flow because power-related issues can affect chip timing and even lead to complete device failure. Specifically, excessive rail voltage drop (IR-drop) and ground bounce can create timing problems and electromigration effects that impact a chip's performance and reliability. Analyzing a chip's power also poses diff... » read more

Design Convergence For 7nm Chips Needs Big Data-Driven Multi-Physics Optimization


Advancements in silicon process technologies are enabling companies to deliver products with faster performance, lower power and greater functionality. These benefits are especially attractive for chip manufacturers servicing markets such as high-end mobile and enterprise computing. However, the cost in terms of both dollars and resources associated with bringing 7-nanometer (nm) finFET-based s... » read more

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