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A New Breed Of EDA Required


While doing research for one of my stories this month, a couple of people basically said that applying methodologies of the past to the designs of today can be problematic because there are fundamental differences in the architectures and workloads. While I completely agree, I don't think these statements go far enough. Designs of today generally have one of everything — one CPU, one accel... » read more

Shifting The Design Paradigm To Improve Verification Efficiency


We are in the midst of a verification crisis manifested by a growing gap between verification efficiency and effectiveness. This crisis cannot be solved through improvements in verification methodologies and techniques alone. Indeed, it requires a philosophical change in the way we approach design, with an emphasis on bug prevention. We refer to this fundamental change as design using intent-fo... » read more

A Price To Be Paid


Ancient wisdom says you should be careful what you ask for, because you just might get it. This was certainly true many times during my career within EDA, and I am sure it is still happening today. Sometimes the outcome was not what was wanted, or the price was higher than expected. As an example, consider VHDL, the language that was meant to correct the problems of Verilog. One of the probl... » read more

Invent A New Way To Do Your Job


My friends own a farm in the southwest of France, and though I spent most of my recent decades around big cities, my village-raised roots are sending me working in the fields every time I have the time. I don’t really care what I’m assigned to, as long as soil, the nearby forest trees, and the sky (preferably blue) will take part. If the job consists of repeating actions, I like to come up ... » read more

Stuck In A Rut


In the DVCon panel session about open-source verification, the first part of which has been published along with this blog, you will read about a fiery debate between the panelists. This is regarding the ability of the EDA industry to innovate. On one side is the accusation that there has been no real innovation since 1988. On the other side, there have been fantastic advances have been made th... » read more

A New Method For Electrical Systems Design


Electrical system complexity is reaching a tipping point across industries, from modern passenger vehicles to sophisticated industrial machines that can now contain nearly 5,000 wiring harnesses. The electrical systems of these machines contain multiple networks, thousands of sensors and actuators, miles of wiring and tens of thousands of discrete components (figure 1). Designing these complex ... » read more

Verification Convergence: Problem Definition


A while ago, I had to go to the ER with my friend who suddenly had a numb feeling in his face. He felt okay (and everything else is okay with him), but better be safe than sorry. While the doctor examined him I noticed that before tracing the problem itself, she asked some questions to rule-out a problem she was already familiar with and that can manifest itself in similar ways. Only then, a... » read more

Customizing Low-Power Platforms Using UPF Dynamic Properties


Low power design and verification engineers need a way to continuously probe various dynamic properties of UPF objects in order to monitor the current state of a verification strategy and utilize that information to develop custom low-power verification environments. Unfortunately, there hasn’t been a reliable, formalized way to do this. Since availability of the dynamic properties of unif... » read more

Clarifying Language/Methodology Confusion


Engineers working on modern, large FPGA designs face multiple challenges: changing languages, methodologies and tools implementing them. The fact that many designs now contain both hardware and software only add to the confusion. This document tries to clarify the situation. Click here to read more. » read more

Importance Of A Functional Verification Methodology


A good functional verification methodology is extremely crucial to the success of any semiconductor design project. Missed or late bugs can massively hurt market share, revenue, and brand name even for reputed companies. The complexity of SoC designs along with tight time-to-market constraints demand high levels of efficiency in the verification process. The approach to verify the functional... » read more

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