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Stuck In A Rut


In the DVCon panel session about open-source verification, the first part of which has been published along with this blog, you will read about a fiery debate between the panelists. This is regarding the ability of the EDA industry to innovate. On one side is the accusation that there has been no real innovation since 1988. On the other side, there have been fantastic advances have been made th... » read more

A New Method For Electrical Systems Design


Electrical system complexity is reaching a tipping point across industries, from modern passenger vehicles to sophisticated industrial machines that can now contain nearly 5,000 wiring harnesses. The electrical systems of these machines contain multiple networks, thousands of sensors and actuators, miles of wiring and tens of thousands of discrete components (figure 1). Designing these complex ... » read more

Verification Convergence: Problem Definition


A while ago, I had to go to the ER with my friend who suddenly had a numb feeling in his face. He felt okay (and everything else is okay with him), but better be safe than sorry. While the doctor examined him I noticed that before tracing the problem itself, she asked some questions to rule-out a problem she was already familiar with and that can manifest itself in similar ways. Only then, a... » read more

Customizing Low-Power Platforms Using UPF Dynamic Properties


Low power design and verification engineers need a way to continuously probe various dynamic properties of UPF objects in order to monitor the current state of a verification strategy and utilize that information to develop custom low-power verification environments. Unfortunately, there hasn’t been a reliable, formalized way to do this. Since availability of the dynamic properties of unif... » read more

Clarifying Language/Methodology Confusion


Engineers working on modern, large FPGA designs face multiple challenges: changing languages, methodologies and tools implementing them. The fact that many designs now contain both hardware and software only add to the confusion. This document tries to clarify the situation. Click here to read more. » read more

Importance Of A Functional Verification Methodology


A good functional verification methodology is extremely crucial to the success of any semiconductor design project. Missed or late bugs can massively hurt market share, revenue, and brand name even for reputed companies. The complexity of SoC designs along with tight time-to-market constraints demand high levels of efficiency in the verification process. The approach to verify the functional... » read more

Methodology Vs. Problem-Solving


When I was 18, I bought a Vespa ’67: the famous Italian scooter. It was already very old then, totally beaten-up, but luckily I had a friend who owned an auto-repair shop, and he was kind enough to give me some access at night. For several weeks, I taught myself the art of metal bodywork, ending up with a beautiful metallic sky-blue ‘67 Vespa. God, I loved that machine! Then one day, ... » read more

Analog Design Needs To Change


It’s an exciting time to be involved in analog design! Innovation in analog design methodology has been flourishing with the introduction of new tools and improved methodologies. And this innovation is badly needed; analog design is getting tougher. Design schedules remain tight, and the technical challenges analog designers face continue to grow – especially when moving to advanced node te... » read more

Three Steps To Faster Low Power Coverage Using UPF 3.0 Information Models


Controlling power has its costs. The added power elements and their interactions make verification of low-power designs much more difficult and the engineer’s job overwhelmingly complex and tedious. Early versions of the Unified Power Format (UPF) provided some relief, but lacked provisions for a standardized methodology for low-power coverage. Ad hoc approaches are error prone and highly ... » read more

Spreadsheets In Virtuoso


The looming tape-out deadline is the nightmare that keeps most design managers up at night. Managing schedules and tracking progress is always a black art that few, if any, can master. Various project management tools and methodologies have been developed that can help, if followed diligently. However, the learning curve of the tools, or the training and overhead of the process, often result in... » read more

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