Author's Latest Posts

Beyond Simulation: Transforming Early IC Design With Insight Analyzer
By Siemens EDA - 06 Feb, 2025 - Comments: 0

Traditional verification methods are proving inadequate for addressing critical reliability challenges in today's increasingly complex integrated circuit (IC) designs. Modern IC design requires a proactive approach to verification that emphasizes early-stage analysis. The shift-left methodology enables earlier identification of potential design risks, addressing the complex challenges of IP blo... » read more

Microsoft Accelerates DRC With Shift-Left Verification
By Siemens EDA - 30 Jan, 2025 - Comments: 0

As integrated circuit (IC) designs grow in complexity, traditional design rule checking (DRC) methods struggle to keep pace. Originally developed for simpler, custom layouts, traditional DRC uses an iterative “construct by correction” method. However, with the rise of automation and multi-layered design hierarchies, relying on traditional sequential DRC approaches can create substantial run... » read more

How Google And Intel Use Calibre DesignEnhancer To Reduce IR Drop And Improve Reliability
By Siemens EDA - 15 Jan, 2025 - Comments: 0

In the fast-paced world of semiconductor design, achieving both Design Rule Check (DRC) clean layouts and optimal electrical performance is crucial for minimizing design iterations, reducing time-to-market and ensuring product reliability. This paper explores how the Calibre DesignEnhancer (DE) analysis-based, signoff-quality EMIR solution helps design teams meet these challenges by enhancing p... » read more

Streaming Scan Network
By Siemens EDA - 14 Jan, 2025 - Comments: 0

Tessent Streaming Scan Network (SSN) is a system for packetized delivery of scan test patterns. It enables simultaneous testing of any number of cores with few chip-level pins, and reduces test time and test data volume. With SSN, DFT engineers have a true SoC DFT solution without compromises between implementation effort and manufacturing test cost. Challenges with DFT for complex SoCs The... » read more

Averting Hacks Of PCIe Transport Using CMA/SPDM
By Siemens EDA - 09 Jan, 2025 - Comments: 0

This paper describes the component measurement and authentication (CMA) and security protocol and data model (SPDM) flow used to establish the secure channels required for the transmission of encrypted packets. The various approaches, namely the symmetric and asymmetric flows, will be discussed in establishing a secure connection with the implementation of CMA/SPDM packets through data objects.... » read more

Calibre DesignEnhancer Design-Stage Layout Modification Improves Power Management Faster And Earlier
By Siemens EDA - 20 Dec, 2024 - Comments: 0

In today’s IC designs, effective power management through layout optimization is crucial for achieving PPA targets. This paper, written by Jeff Wilson, describes how the Calibre DesignEnhancer platform, is used to specifically tackle the EMIR components of power management. DesignEnhancer offers P&R and custom/analog design teams a fast, integrated environment for implementing Calibre-cle... » read more

Verifying SRAM Yield Inclusive Of Rare And Random Defects
By Siemens EDA - 11 Dec, 2024 - Comments: 0

Large disparities were observed between wafer level SRAM Access Disturb related bit-fails as measured on silicon wafers and the number of such bit-fails as predicted by intrinsic device variability alone. Root cause investigations pointed to a rare but random defect lowering threshold voltage of the NFET devices of the SRAM bit-cell. This work presents a novel method to enable the inclusion of ... » read more

ESD Verification For 2.5D And 3D-ICs
By Siemens EDA - 10 Dec, 2024 - Comments: 0

Ensuring your integrated circuit (IC) design can withstand electrostatic discharge (ESD) events without incurring damage or failure is an extremely important activity in IC circuit design and verification. While automated flows for ESD verification are well-established for regular 2D ICs, 2.5D and 3D integration presents new challenges in both ESD design and verification. The new automated ESD ... » read more

The Xpedition Flow
By Siemens EDA - 26 Nov, 2024 - Comments: 0

Comprehensive approach to designing electronics The complexities of modern PCB design necessitate a comprehensive approach that integrates various aspects of the entire design through manufacturing flow. The ideal design flow requires seamless cooperation and synergy across various domains, including electrical, mechanical, software, systems, test, and manufacturing. Xpedition provides a gr... » read more

Accelerating Verification Of Computational Storage Designs Using Avery NVMe Verification IP
By Siemens EDA - 14 Nov, 2024 - Comments: 0

Computational storage is an emerging paradigm that integrates processing capabilities directly within storage devices. This paper outlines how this approach addresses the limitations of traditional NVM Express (NVMe) SSDs and the performance characteristics of the newly introduced compute and subsystem local memory (SLM) namespaces. The paper also focuses on the verification framework provided ... » read more

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