Author's Latest Posts

Averting Hacks Of PCIe Transport Using CMA/SPDM
By Siemens EDA - 09 Jan, 2025 - Comments: 0

This paper describes the component measurement and authentication (CMA) and security protocol and data model (SPDM) flow used to establish the secure channels required for the transmission of encrypted packets. The various approaches, namely the symmetric and asymmetric flows, will be discussed in establishing a secure connection with the implementation of CMA/SPDM packets through data objects.... » read more

Calibre DesignEnhancer Design-Stage Layout Modification Improves Power Management Faster And Earlier
By Siemens EDA - 20 Dec, 2024 - Comments: 0

In today’s IC designs, effective power management through layout optimization is crucial for achieving PPA targets. This paper, written by Jeff Wilson, describes how the Calibre DesignEnhancer platform, is used to specifically tackle the EMIR components of power management. DesignEnhancer offers P&R and custom/analog design teams a fast, integrated environment for implementing Calibre-cle... » read more

Verifying SRAM Yield Inclusive Of Rare And Random Defects
By Siemens EDA - 11 Dec, 2024 - Comments: 0

Large disparities were observed between wafer level SRAM Access Disturb related bit-fails as measured on silicon wafers and the number of such bit-fails as predicted by intrinsic device variability alone. Root cause investigations pointed to a rare but random defect lowering threshold voltage of the NFET devices of the SRAM bit-cell. This work presents a novel method to enable the inclusion of ... » read more

ESD Verification For 2.5D And 3D-ICs
By Siemens EDA - 10 Dec, 2024 - Comments: 0

Ensuring your integrated circuit (IC) design can withstand electrostatic discharge (ESD) events without incurring damage or failure is an extremely important activity in IC circuit design and verification. While automated flows for ESD verification are well-established for regular 2D ICs, 2.5D and 3D integration presents new challenges in both ESD design and verification. The new automated ESD ... » read more

The Xpedition Flow
By Siemens EDA - 26 Nov, 2024 - Comments: 0

Comprehensive approach to designing electronics The complexities of modern PCB design necessitate a comprehensive approach that integrates various aspects of the entire design through manufacturing flow. The ideal design flow requires seamless cooperation and synergy across various domains, including electrical, mechanical, software, systems, test, and manufacturing. Xpedition provides a gr... » read more

Accelerating Verification Of Computational Storage Designs Using Avery NVMe Verification IP
By Siemens EDA - 14 Nov, 2024 - Comments: 0

Computational storage is an emerging paradigm that integrates processing capabilities directly within storage devices. This paper outlines how this approach addresses the limitations of traditional NVM Express (NVMe) SSDs and the performance characteristics of the newly introduced compute and subsystem local memory (SLM) namespaces. The paper also focuses on the verification framework provided ... » read more

Preparing For The Multiphysics Future Of 3D ICs
By Siemens EDA - 07 Nov, 2024 - Comments: 0

3D integrated circuits (3D ICs) are emerging as a revolutionary approach to design, manufacturing and packaging in the semiconductor industry. Offering significant advantages in size, performance, power efficiency and cost, 3D ICs are poised to transform the landscape of electronic devices. However, with 3D ICs come new design and verification challenges that must be addressed to ensure success... » read more

Shift Left The Design Process With Calibre Interactive Symmetry Checking
By Siemens EDA - 16 Oct, 2024 - Comments: 0

The traditional methods of symmetry checking are due for an update. The Calibre interactive, no code symmetry checking solution helps designers capture symmetry issues very early in the design cycle to reduce the number of iterations. Calibre interactive symmetry checking shifts left the whole verification process and reduces the time needed to reach tape out. What you’ll learn: Why the... » read more

Signal Integrity Basics
By Siemens EDA - 26 Sep, 2024 - Comments: 0

In this orientation to signal integrity basics, we aim to introduce several important and fundamental concepts of signal integrity for the beginner. Most explanations are provided at a high level without a lot of depth and math, and examples are provided with a focus on comparison rather than detailed numerical results. Of course, background depth, math, and numerical details are very important... » read more

On Analysis Of RDC Issues For Identifying Reset Tree Design Bugs And Further Strategies For Noise Reduction
By Siemens EDA - 12 Sep, 2024 - Comments: 0

Reset tree checks should be viewed thoroughly before reset domain crossing analysis. Static verification tools have many checks for reset tree analysis. This paper discusses the usage of non-resettable registers (NRRs) in reset paths. NRRs can cause metastability in the reset paths and hence thorough verification is a must. The paper discusses reduction of false failure reporting noise strategi... » read more

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