Author's Latest Posts


Complete Reliability Verification For Multiple-Power-Domain Designs


With increasing design complexity and a heightened focus on reliability at all levels of integrated circuit (IC) design from intellectual property (IP) to full-chip, accurate and full verification coverage of the different reliability concerns within an IC design is essential. Designs containing multiple power domains add more complexity to reliability verification with the need to validate int... » read more

How Do You Qualify Tools For DO-254 Programs?


This paper describes the terminology and requirements related to tool qualification specific to the safety-critical programs governed by DO-254 compliance. It also provides some practical examples of tool qualification processes and strategies for commonly used tools. Qualifying tools for DO-254 While the use of state-of-the art development tools has led to ever increasing design complexity... » read more

Addressing SRAM Verification Challenges


SureCore Limited is an SRAM IP company based in Sheffield, the United Kingdom, that develops low power memories for current and next generation silicon process technologies. Its award-winning, world-leading, low power SRAM designs are process independent and variability tolerant, making them suitable for a wide range of technology nodes. Two major product families have been announced: PowerM... » read more

Similar But Different — The Tale Of Transient And Permanent Faults


When determining whether an IC is safe from random hardware faults, applying safety metrics such as PMHF, SPFM, and LFM, engineers must analyze both transient and permanent faults. This paper highlights the fundamental differences between permanent and transient faults on digital circuits, and why this distinction is important in the context of the ISO 26262:2018 functional safety standard. ... » read more

Interactive Symmetry Checking Provides Faster, Easier Symmetry Verification For Analog And Custom IC Designs


Device symmetry ensures accurate, efficient performance of analog and custom IC designs. However, traditional physical verification for symmetry is complex and time-consuming. Calibre interactive symmetry checking runs inside the design environment to simplify and enhance IC symmetry verification. Design teams can use Calibre interactive symmetry checking to quickly and accurately analyze layou... » read more

Interactive Point-To-Point Resistance Simulations


Point to point (P2P) resistance simulations calculate the effective resistance of the layout traces between points on an IC net trace, and let the designer know that there may be too much parasitic resistance from a particular net trace that would affect the reliability or performance of the circuit. However, traditional P2P simulation runs are time-consuming, and often require multiple iterati... » read more

Affordable And Comprehensive Testing Of 3D Stacked Die Devices


Developers of high-end semiconductor products who face manufacturing limitations with respect to die sizes are investing in 3D stacked die technology. These advanced designs already push current design-for-test (DFT) solutions to the limits: tool run time, on-chip area demand, test pattern count, and test time. How then, can designers manage DFT for these new 3D devices? In this paper, we outli... » read more

Enabling Model-Based Design For DO-254 Certification Compliance


The increasing prevalence and cost of projects that need to comply with the DO-254 standard is forcing companies to evaluate their development processes. This white paper shows a development approach to compliance using model-based design. It covers how a DO-254 workflow using model-based design promotes a consistent requirements-oriented project view and increases reuse of design and verificat... » read more

Ensure Functional Safety Using Siemens’ AUTOSAR Solutions


As the prevalence of automated driving, electrification, and connected vehicle applications increases, the complexity of electrical and electronic (E/E) vehicle architecture is increasing, and vehicle safety requirements are becoming more demanding. Solution architects and engineers are looking for ways to manage it all. And they can, with the help of our comprehensive AUTOSAR solution that pro... » read more

Power Methodology For Estimation And Optimization In The ASIC/SoC Flow


In this white paper, we’ll review the many steps of today’s common ASIC/SoC power methodologies and tool flows. We’ll then propose ways you can further optimize your power methodology to more quickly achieve your PPW goals. Please note, while we acknowledge that energy consumption in digital CMOS logic is a combination of dynamic power and leakage, to keep this white paper to a digestible... » read more

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