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Multi-Die Design Start Guide
By Synopsys - 23 Apr, 2025 - Comments: 0

If you are exploring a multi-die project and need guidelines on getting started, this white paper is for you. Any engineer on a semiconductor design project has read many articles about the power, performance, and area (PPA), functional scalability, and time-to-market advantages of multi-die designs using 2.5D and 3D technologies. The advantages are the main reason the adoption of multi-die des... » read more

Advanced Atomistic Simulation Techniques For Atomic Layer Etching
By Synopsys - 17 Apr, 2025 - Comments: 0

Continuous downscaling of the critical dimensions in semiconductor devices is the cornerstone of technological revolution. As the technology nodes keep shrinking, innovations in fabrication technologies are needed to continue the trend. We have arrived at the age where atomic level precision in the fabrication of semiconductor devices is needed to keep improving PPA. Thus, advanced film fabrica... » read more

2024 Security IP Year In Review: Innovations And Best Practices
By Synopsys - 03 Apr, 2025 - Comments: 0

This booklet offers six insightful articles on advanced security IP technologies, helping to fortify digital systems against emerging threats. Learn about: DDR Interface Security: Defend against DRAM attacks. IoT Security: Safeguard IoT devices with SIM and Root of Trust. SRAM PUF Technology: Secure device authentication. Post-Quantum Cryptography: Protect against quantum threa... » read more

Virtualizer Native Execution Accelerates Software Defined Product Development for Arm Solutions
By Synopsys - 26 Mar, 2025 - Comments: 0

This whitepaper highlights advancements in virtual prototyping with near native execution performance. The adoption of Arm processor architecture in automotive and data centers is driven by software complexity and ECU consolidation. This shift elevates virtualization performance requirements, supported by Arm's mature software ecosystem. Key Takeaways: Adoption of and convergence of bot... » read more

LLE-Aware Design Methodology To Avoid Timing And Power Pessimism
By Synopsys - 12 Mar, 2025 - Comments: 0

As chips move to ever-finer geometries, the active region (diffusion) shapes of neighboring cells can impact timing analysis and power calculations for the entire design. The LLE (Local Layout Effect) impact must be measured, but the impact is reflected very conservatively using conventional approaches. This paper describes a LLE-aware design methodology that mitigates the conservatism of co... » read more

Secure Interfaces for Critical Semiconductor Applications
By Synopsys - 06 Mar, 2025 - Comments: 0

Security is now a concern for nearly all semiconductors in nearly all applications. Once of high interest mostly for military and financial systems, both the increasingly connected world and the plethora of existing security threats have changed the landscape dramatically. Every aspect of electronic system design—hardware, firmware, and software—has its own sets of risks and requirements to... » read more

Pre-Silicon Verification Of Die-to-Die IP With Novel ESD Protection
By Synopsys - 26 Feb, 2025 - Comments: 0

All major foundries have adopted the programmable electrical rule checker (PERC) as the pre-silicon electrostatic discharge (ESD) signoff tool for IP and chip designs. This concept of rule checking works fine for most IP types, but for die-to-die IP, used in 3DIC designs, the PERC approach may not be appropriate. Die-to-die interface IP includes extremely large numbers of I/Os, trending towards... » read more

Why HPC Chip Designers Are Looking Into Linear Pluggable Optics
By Synopsys - 12 Feb, 2025 - Comments: 0

This paper delves into the technical complexities and emerging trends in integrating linear pluggable optics within AI chip design. The rapid growth of hyperscale data centers, driven by the demands of LLMs and transformative AI applications, requires innovative solutions optimized for power, latency, and bandwidth. Emerging industry standards are ensuring interoperability between independently... » read more

Securing FPGAs Beyond the Bitstream
By Synopsys - 06 Feb, 2025 - Comments: 0

FPGAs are a popular solution for low-volume applications and applications where frequent updates are essential to the value of the solution, as in many aerospace and defense and AI applications. Security is a critical part of FPGA solutions, and FPGA providers have invested much effort into securing the bitstream. However, there is a need for a cryptographic solution for FPGAs beyond the bitstr... » read more

Achieving Successful Timing, Power, And Physical Signoff For Multi-Die Designs
By Synopsys - 15 Jan, 2025 - Comments: 0

Multi-die designs using 2.5D and 3D technologies are increasingly important for a wide range of electronics applications, including high-performance computing (HPC), artificial intelligence (AI), automotive, and mobile. The multi-die architecture enables designers to mix dies from different foundries and technology nodes, including existing dies from previous projects. The resulting density and... » read more

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