Author's Latest Posts

Curvilinear Mask Patterning For Maximizing Lithography Entitlement
By Synopsys - 15 Nov, 2023 - Comments: 0

Curvilinear Mask Patterning is a cutting-edge lithography technique that promises to maximize lithography entitlement by addressing complex design challenges and critical yield limiters. However, its widespread deployment has been limited by significant computational challenges. This paper includes practical solutions to overcome the computational challenges associated with this technique, as w... » read more

Automated Constraint Management For Faster Designer Productivity
By Synopsys - 07 Nov, 2023 - Comments: 0

Constraints management helps shorten the designer’s manual constraints transformation effort across the design cycle with automated constraints management flows. The management of constraints refers to tasks that are not associated with verifying the correctness of constraints, nor associated with the generation of constraints, but with the transformation of constraints from one form to anoth... » read more

2023 Open Source Security And Risk Analysis Report
By Synopsys - 01 Nov, 2023 - Comments: 0

The annual “Open Source Security and Risk Analysis” (OSSRA) report, now in its 8th edition, examines vulnerabilities and license conflicts found in roughly 1,700 codebases across 17 industries. The report offers recommendations for security, legal, risk, and development teams to better understand the security and risk landscape accompanying open source development and use. Click here to ... » read more

ESD Co-Design For 224G And 112G SerDes In FinFET Technologies
By Synopsys - 25 Oct, 2023 - Comments: 0

In addressing the challenges of enhancing ESD resilience for high-speed SerDes interfaces, it's crucial to ensure the implementation of appropriate ESD protection measures. This is particularly vital during the device's lifecycle from the conclusion of silicon wafer processing to system assembly, a phase during which electronic devices are highly susceptible to Electrostatic Discharge (ESD) dam... » read more

How Multi-Die Systems Are Transforming Electronic Design
By Synopsys - 11 Oct, 2023 - Comments: 0

How can the electronics industry continue as Moore’s law slows, system complexity increases, and the number of transistors balloons to trillions? Multi-die systems have emerged as the solution to go beyond Moore’s law and address the challenges of systemic complexity, allowing for accelerated, cost-effective scaling of system functionality, reduced risk and time to market, lower system p... » read more

How Quickly Will Multi-Die Systems Change Semiconductor Design?
By Synopsys - 04 Oct, 2023 - Comments: 0

For many decades, semiconductor design and implementation has been focused on monolithic, ever-larger and more complex single-chip implementation. This system-on-chip approach is now changing for a variety of reasons. The new frontier utilizes many chips assembled in new ways to deliver the required form-factor and performance. Multi-die systems are paving the way for new types of semiconduc... » read more

Universal Verification Methodology Coverage For Bluespec RISC-V Cores
By Synopsys - 27 Sep, 2023 - Comments: 0

Attempting to achieve complete RISC-V verification requires multiple methodologies, one of which is coverage driven simulation based on UVM constrained random methods and complaint with the Universal Verification Methodology (UVM) standard. This whitepaper explains the basics of UVM functional coverage for RISC-V cores using the Google RISCV-DV open-source project, Synopsys verification solu... » read more

Understanding UVM Coverage For RISC-V Processor Designs
By Synopsys - 13 Sep, 2023 - Comments: 0

Attempting to achieve complete RISC-V verification requires multiple methodologies employing a wide range of relevant tools, including: • Coverage driven simulation based on UVM constrained random methods and compliant with the Universal Verification Methodology (UVM) standard • Static and formal property verification • Equivalence checking • Emulation and FPGA based verific... » read more

Synopsys Timing Constraints Manager: Constraint Verification
By Synopsys - 11 Sep, 2023 - Comments: 0

Constraint verification refers to the verification of the contents of an SDC file to flag situations where the specified constraints are either incorrect, or incomplete, both of which, if not addressed, could result in silicon failure. The key to constraint verification is the ability to flag real issues without swamping an engineer with noise: issues that upon designer review result in no chan... » read more

A Perfect Blend Of Quality In Functional Safety To Accelerate An Automotive IP Product Release
By Synopsys - 06 Sep, 2023 - Comments: 0

The integration of functional safety and quality into the automotive development process is crucial for ensuring the safety and reliability of vehicles on the road. Automotive manufacturers must take a comprehensive approach to both functional safety and quality, considering all aspects of the vehicle from design to production and beyond. This includes the use of advanced technologies s... » read more

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