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Understanding UVM Coverage For RISC-V Processor Designs
By Synopsys - 13 Sep, 2023 - Comments: 0

Attempting to achieve complete RISC-V verification requires multiple methodologies employing a wide range of relevant tools, including: • Coverage driven simulation based on UVM constrained random methods and compliant with the Universal Verification Methodology (UVM) standard • Static and formal property verification • Equivalence checking • Emulation and FPGA based verific... » read more

Synopsys Timing Constraints Manager: Constraint Verification
By Synopsys - 11 Sep, 2023 - Comments: 0

Constraint verification refers to the verification of the contents of an SDC file to flag situations where the specified constraints are either incorrect, or incomplete, both of which, if not addressed, could result in silicon failure. The key to constraint verification is the ability to flag real issues without swamping an engineer with noise: issues that upon designer review result in no chan... » read more

A Perfect Blend Of Quality In Functional Safety To Accelerate An Automotive IP Product Release
By Synopsys - 06 Sep, 2023 - Comments: 0

The integration of functional safety and quality into the automotive development process is crucial for ensuring the safety and reliability of vehicles on the road. Automotive manufacturers must take a comprehensive approach to both functional safety and quality, considering all aspects of the vehicle from design to production and beyond. This includes the use of advanced technologies s... » read more

Power Supply Noise Effects On Jitter In Clock Synchronous Systems With Emphasis On Memory Interfaces
By Synopsys - 23 Aug, 2023 - Comments: 0

In today's fast-paced digital world, the performance and capacity of high-speed memory has become crucial for a wide range of applications, from personal computing devices to data centers and high-performance computing systems. Designers face challenges in optimizing their designs for speed, power efficiency, and reliability — all while ensuring robustness in the face of power supply noise. T... » read more

Power Supply Noise Effects On Jitter In Clock Synchronous Systems With Emphasis On Memory Interfaces
By Synopsys - 09 Aug, 2023 - Comments: 0

Power Supply Noise Effects on Jitter in Clock Synchronous Systems with Emphasis on LPDDR5X, DDR5 and HBM3 In today's fast-paced digital world, the performance and capacity of high-speed memory has become crucial for a wide range of applications, from personal computing devices to data centers and high-performance computing systems. Designers face challenges in optimizing their designs ... » read more

FMEDA Powered Safety Verification Methodology For Semiconductors
By Synopsys - 08 Aug, 2023 - Comments: 0

Today’s automobiles require increasingly complex systems and chips, adherence to functional safety processes has become essential during the design development phase. The intricate nature of  semiconductors used in automotive applications is driving the need for functional safety throughout the entire supply chain, reaching not just the automobile manufacturers but also the semiconductor des... » read more

Solving the AppSec Puzzle: Connecting AppSec To Your DevOps Pipeline
By Synopsys - 02 Aug, 2023 - Comments: 0

Integrating application security (AppSec) into your software development life cycle and DevOps pipeline is increasingly important in today’s development environment. Commonly referred to as “shifting left” or “shifting everywhere,” AppSec integration helps avoid the late-stage testing and development that can delay product releases or lead to overlooked risks being promoted into produ... » read more

An Automated Method For Adding Resiliency To Mission-Critical SoC Designs
By Synopsys - 21 Jun, 2023 - Comments: 0

Adding safety measures to system-on-chip (SoC) designs in the form of radiation-hardened elements or redundancy is essential in making mission-critical applications in the Aerospace and Defense (A&D), cloud, automotive, robotics, medical, and Internet-of-Things (IoT) industries more resilient against random hardware failures that occur. Designing for reliable and resilient functionality doe... » read more

ESD Co-Design For High-Speed SerDeS In FinFET Technologies
By Synopsys - 07 Jun, 2023 - Comments: 0

An electronic device is susceptible to Electrostatic Discharge (ESD) damage during its entire life cycle, including the phase from the completion of the silicon wafer processing to when the device (die) is assembled in the system. To avoid yield loss due to ESD damage during this early phase, on-chip ESD protection measures are applied to provide a certain degree of ESD robustness. The componen... » read more

Accelerating Development of Software Defined Vehicles with Virtual ECUs
By Synopsys - 31 May, 2023 - Comments: 0

The automotive industry is going through a revolution. To adapt to new customer demands such as convenience, safety, autonomy, and electrification, the automotive industry is moving to software-driven vehicles. These require new, more powerful electrical/electronic (E/E) architectures and significantly increase the vehicle software content. They also force the industry to move from lengthy deve... » read more

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