Author's Latest Posts

Pre-Silicon Hardware Trojans: Design, Benchmarking, Detection And Prevention (Sandia Labs)
By Technical Paper Link - 09 Apr, 2025 - Comments: 0

A new technical paper titled "A Survey on the Design, Detection, and Prevention of Pre-Silicon Hardware Trojans" was published by researchers at Sandia National Laboratories. "In this survey, we first highlight efforts in Trojan design and benchmarking, followed by a cataloging of seminal and recent works in Trojan detection and prevention and their accompanied metrics. Given the volume of l... » read more

GenAI for Analog IC Design (McMaster University)
By Technical Paper Link - 08 Apr, 2025 - Comments: 0

A new technical paper titled "Generative AI for Analog Integrated Circuit Design: Methodologies and Applications" was published by researchers at McMaster University. Abstract "Electronic Design Automation (EDA) in analog Integrated Circuits (ICs) has been the focus of extensive research; however, unlike its digital counterpart, it has not achieved widespread adoption. In this systematic re... » read more

2D Materials Roadmap: Current And Future Challenges, Solutions
By Technical Paper Link - 08 Apr, 2025 - Comments: 0

A new technical paper titled "The 2D Materials Roadmap" was published by researchers at many institutions including Chinese Academy of Sciences, TU Denmark, Pennsylvania State University, University of Manchester, University of Cambridge et al. Abstract "Over the past two decades, 2D materials have rapidly evolved into a diverse and expanding family of material platforms. Many members of th... » read more

Cache Coherence In Network On Chip Design (NTU)
By Technical Paper Link - 08 Apr, 2025 - Comments: 0

A new technical paper titled "Learning Cache Coherence Traffic for NoC Routing Design" was published by researchers at Nanyang Technological University. "In this work, we propose a cache coherence-aware routing approach with integrated topology selection, guided by our Cache Coherence Traffic Analyzer (CCTA). Our method achieves up to 10.52% lower packet latency, 55.51% faster execution time... » read more

Countermeasure Against Confidentiality And Integrity Attacks On Hardware IP (U. of Florida)
By Technical Paper Link - 08 Apr, 2025 - Comments: 0

A new technical paper titled "HIPR: Hardware IP Protection through Low-Overhead Fine-Grain Redaction" was published by researchers at University of Florida. Abstract "Hardware IP blocks have been subjected to various forms of confidentiality and integrity attacks in recent years due to the globalization of the semiconductor industry. System-on-chip (SoC) designers are now considering a zero... » read more

Scalable Approach For Fabricating Sub-10nm Nanogaps
By Technical Paper Link - 07 Apr, 2025 - Comments: 0

A new technical paper titled "A progressive wafer scale approach for Sub-10 nm nanogap structures" was published by researchers at Seoul National University, Chung-Ang University, Mohammed VI Polytechnic University and Ulsan National Institute of Science and Technology. "We have advanced the atomic layer lithography method into an efficient, scalable approach for fabricating sub-10 nm nanoga... » read more

Side-by-Side Benchmark of NPU Platforms (Imperial College London, Cambridge)
By Technical Paper Link - 05 Apr, 2025 - Comments: 0

A new technical paper titled "Benchmarking Ultra-Low-Power μNPUs" was published by researchers at Imperial College London and University of Cambridge. Abstract "Efficient on-device neural network (NN) inference has various advantages over cloud-based processing, including predictable latency, enhanced privacy, greater reliability, and reduced operating costs for vendors. This has sparked t... » read more

Study Of Multi-Die And Multi-Technology Floorplanning (Texas A&M, Duke)
By Technical Paper Link - 05 Apr, 2025 - Comments: 0

A new technical paper titled "PPAC Driven Multi-die and Multi-technology Floorplanning" was published by Texas A&M University and Duke University. Abstract "In heterogeneous integration, where different dies may utilize distinct technologies, floorplanning across multiple dies inherently requires simultaneous technology selection. This work presents the first systematic study of multi-die ... » read more

Emerging Cybersecurity Risks in Connected Vehicles, With Focus On In-Vehicle and Vehicle-Edge Platforms
By Technical Paper Link - 04 Apr, 2025 - Comments: 0

A new technical paper titled "Security Risks and Designs in the Connected Vehicle Ecosystem: In-Vehicle and Edge Platforms" was published by researchers at Università di Pisa, Ford Motor Company, MIT, and the Institute of Informatics and Telematics (Pisa). Abstract "The evolution of Connected Vehicles (CVs) has introduced significant advancements in both in-vehicle and vehicle-edge platfor... » read more

Thermal Slip Length at a L/S Interface: Power Law Relations From Spatial and Frequency Attributes of the Contact Layer (Caltech)
By Technical Paper Link - 04 Apr, 2025 - Comments: 0

A new technical paper titled "Thermal Slip Length at a Liquid/Solid Interface: Power Law Relations From Spatial and Frequency Attributes of the Contact Layer" was published by researchers at California Institute of Technology, , T. J. Watson Sr. Laboratories of Applied Physics. Abstract "Specialty integrated chips for power intensive tasks like artificial intelligence generate so much heat ... » read more

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