Author's Latest Posts

FOWLP Warpage: Review Of Causes, Modeling And Methodologies For Controlling
By Technical Paper Link - 14 Feb, 2025 - Comments: 0

A new technical paper titled "Warpage in wafer-level packaging: a review of causes, modelling, and mitigation strategies" was published by researchers at Arizona State University. Abstract "Wafer-level packaging (WLP) is a pivotal semiconductor packaging technology that enables heterogeneously integrated advanced semiconductor packages with high-density electrical interconnections through i... » read more

Demonstration Of An ALD IWO Channel In A GAA Nanosheet FET Structure (Georgia Tech, Micron)
By Technical Paper Link - 14 Feb, 2025 - Comments: 0

A new technical paper titled "First Demonstration of High-Performance and Extremely Stable W-Doped In2O3  Gate-All-Around (GAA) Nanosheet FET" was published by researchers at Georgia Institute of Technology and Micron. Abstract "We demonstrate a gate-all-around (GAA) nanosheet FET featuring an atomic layer-deposited (ALD) tungsten (W)-doped indium oxide (In2O3), or indium tungsten oxide ... » read more

Uncore Frequency Scaling For Energy Optimization In Heterogeneous Systems (UIC, Argonne)
By Technical Paper Link - 12 Feb, 2025 - Comments: 0

A new technical paper titled "Exploring Uncore Frequency Scaling for Heterogeneous Computing" was published by researchers at University of Illinois Chicago and Argonne National Laboratory. Abstract "High-performance computing (HPC) systems are essential for scientific discovery and engineering innovation. However, their growing power demands pose significant challenges, particularly as sys... » read more

Simulation Study Of Vertically Stacked 2D NSFETs
By Technical Paper Link - 12 Feb, 2025 - Comments: 0

A new technical paper titled "Simulation of Vertically Stacked 2-D Nanosheet FETs" was published by researchers at Università di Pisa and TU Wien. Abstract "We present a simulation study of vertically stacked 2-D nanosheet field-effect transistors (NSFETs). The aim of this investigation is to assess the performance and potential of FinFET alternatives, i.e., gate-all-around (GAA) nanosheet... » read more

Rowhammer Mitigation With Adaptive Refresh Management Optimization (KAIST, Sk hynix)
By Technical Paper Link - 12 Feb, 2025 - Comments: 0

A new technical paper titled "Securing DRAM at Scale: ARFM-Driven Row Hammer Defense with Unveiling the Threat of Short tRC Patterns" was published by researchers at KAIST and Sk hynix. Abstract (partial) "To address the issue of powerful row hammer (RH) attacks, our study involved an extensive analysis of the prevalent attack patterns in the field. We discovered a strong correlation betwee... » read more

High-Temperature Nonreciprocal Thermal Radiative Properties From Semiconductors (U. Houston, Caltech, UW-Madison)
By Technical Paper Link - 12 Feb, 2025 - Comments: 0

A new technical paper titled "High-Temperature Strong Nonreciprocal Thermal Radiation from Semiconductors" was published by University of Houston, California Institute of Technology and University of Wisconsin-Madison. Abstract "Nonreciprocal thermal emitters that break the conventional Kirchhoff's law allow independent control of emissivity and absorptivity and promise exciting new funct... » read more

Maximizing Energy Efficiency in Subthreshold RISC-V Cores (NTNU)
By Technical Paper Link - 12 Feb, 2025 - Comments: 0

A new technical paper titled "Optimizing Energy Efficiency in Subthreshold RISC-V Cores" was published by researchers at Norwegian University of Science and Technology (NTNU). Abstract "Our goal in this paper is to understand how to maximize energy efficiency when designing standard-ISA processor cores for subthreshold operation. We hence develop a custom subthreshold library and use it to ... » read more

Wafer-Scale Computing for LLMs (U. of Edinburgh, Microsoft)
By Technical Paper Link - 09 Feb, 2025 - Comments: 0

A new technical paper titled "WaferLLM: A Wafer-Scale LLM Inference System" was published by researchers at University of Edinburgh and Microsoft Research. Abstract "Emerging AI accelerators increasingly adopt wafer-scale manufacturing technologies, integrating hundreds of thousands of AI cores in a mesh-based architecture with large distributed on-chip memory (tens of GB in total) and ultr... » read more

Potential of Wireless Interconnects For Improving Performance And Flexibility Of Multi-Chip AI Accelerators
By Technical Paper Link - 07 Feb, 2025 - Comments: 0

A new technical paper titled "Exploring the Potential of Wireless-enabled Multi-Chip AI Accelerators" was published by researchers at Universitat Politecnica de Catalunya. Abstract "The insatiable appetite of Artificial Intelligence (AI) workloads for computing power is pushing the industry to develop faster and more efficient accelerators. The rigidity of custom hardware, however, conflict... » read more

Power Delivery Challenges in 3D HI CIM Architectures for AI Accelerators (Georgia Tech)
By Technical Paper Link - 07 Feb, 2025 - Comments: 0

A new technical paper titled "Co-Optimization of Power Delivery Network Design for 3D Heterogeneous Integration of RRAM-based Compute In-Memory Accelerators" was published by researchers at Georgia Tech. Abstract: "3D heterogeneous integration (3D HI) offers promising solutions for incorporating substantial embedded memory into cutting-edge analog compute-in-memory (CIM) AI accelerators, ad... » read more

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