Author's Latest Posts

Accelerator Architecture For In-Memory Computation of CNN Inferences Using Racetrack Memory
By Technical Paper Link - 03 Jul, 2025 - Comments: 0

A new technical paper titled "Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems" was published by researchers at National University of Singapore, A*STAR, Chinese Academy of Sciences, and Hong Kong University of Science and Technology. Abstract "Deep neural networks generate and process large volumes of data, posing challe... » read more

Development and Deployment of 2.5D Multi-Foundry Chiplet Solution Scaling Beyond Multi-Reticle Approaches (Intel)
By Technical Paper Link - 03 Jul, 2025 - Comments: 0

A new technical paper titled "System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution" was published by researchers at Intel Corporation. Abstract "The proliferation of chiplet-based designs, driven by the escalating computational demands of AI, presents unique validation challenges when integrating heterogenous chiplets. This paper investigat... » read more

Framework To Analyze Threats To The Semiconductor Supply Chain (NIST, U. of Maryland)
By Technical Paper Link - 03 Jul, 2025 - Comments: 0

A new technical paper titled "Analyzing Collusion Threats in the Semiconductor Supply Chain" was published by researchers at NIST and University of Maryland. Abstract "This work proposes a framework for analyzing threats related to the semiconductor supply chain. The framework introduces a metric that quantifies the severity of different threats subjected to a collusion of adversaries from ... » read more

HW Security: A Hybrid Verification Method Combining Simulation And Formal Verification (RPTU, UCSD)
By Technical Paper Link - 01 Jul, 2025 - Comments: 0

A new technical paper titled "FastPath: A Hybrid Approach for Efficient Hardware Security Verification" was published by researchers at RPTU Kaiserslautern-Landau and UC San Diego. "We propose FastPath, a hybrid verification methodology that combines the efficiency of simulation with the exhaustive nature of formal verification. FastPath employs a structural analysis framework to automate th... » read more

Data-Driven Approach To Power Modeling For DVFS-Enabled Heterogeneous Systems (ETH Zurich et al.)
By Technical Paper Link - 01 Jul, 2025 - Comments: 0

A technical paper titled "Data-driven power modeling and monitoring via hardware performance counter tracking" was published by researchers at ETH Zürich, Scuola Superiore Sant’Anna, RISE Research Institutes of Sweden and University of Bologna. Abstract "Energy-centric design is paramount in the current embedded computing era: use cases require increasingly high performance at an afforda... » read more

Stacking Persistent Embedded Memories Based On Oxide Transistors Upon GPGPU Platforms (Georgia Tech)
By Technical Paper Link - 01 Jul, 2025 - Comments: 0

A new technical paper titled "CMOS+X: Stacking Persistent Embedded Memories based on Oxide Transistors upon GPGPU Platforms" was published by Georgia Tech. Abstract "In contemporary general-purpose graphics processing units (GPGPUs), the continued increase in raw arithmetic throughput is constrained by the capabilities of the register file (single-cycle) and last-level cache (high bandwidth... » read more

High-Performance p-type 2D FETs By Nitric Oxide Doping (Penn State)
By Technical Paper Link - 01 Jul, 2025 - Comments: 0

A new technical paper titled "High-performance p-type bilayer WSe2 field effect transistors by nitric oxide doping" was published by researchers at Penn State University and Florida International University. Abstract "Two-dimensional (2D) materials are promising candidates for next-generation electronics, but the realization of high-performance p-type 2D field-effect transistors (FETs) has... » read more

Patterned MW-NSFETs For Sustainable Scaling (POSTECH)
By Technical Paper Link - 28 Jun, 2025 - Comments: 0

A new technical paper titled "Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut Width" was published by researchers at POSTECH. Abstract "In nanosheet field-effect transistors (NSFETs), the scaling of the cell height (CH) is constrained by strict design rules related to gate extension (GE), gate cut (GC), and device-to-device distance. ... » read more

Viability of aZnMIm As A Resist For EUV Lithography (Johns Hopkins, Northwestern, Intel et al.)
By Technical Paper Link - 27 Jun, 2025 - Comments: 0

A new technical paper (preprint) titled "Extreme Ultraviolet and Beyond Extreme Ultraviolet Lithography using Amorphous Zeolitic Imidazolate Resists Deposited by Atomic/Molecular Layer Deposition" was published by researchers at Johns Hopkins University, Northwestern University, Intel Corporation, Bruker Nano, EUV Tech and Lawrence Berkeley National Lab. The paper states "This study demonstr... » read more

GNN-Based Framework for Hardware Trojan Detection, Including RISC-V Cores
By Technical Paper Link - 26 Jun, 2025 - Comments: 0

A new technical paper titled "TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs" was published by researchers at University of Connecticut and University of Minnesota. Abstract "hip manufacturing is a complex process, and to achieve a faster time to market, an increasing number of untrusted third-party tools and designs from around the world are being utilized. The use of th... » read more

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