Author's Latest Posts


Gemmini: Open-source, Full-Stack DNN Accelerator Generator (DAC Best Paper)


This technical paper titled "Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration" was published jointly by researchers at UC Berkeley and a co-author from MIT.  The research was partially funded by DARPA and won DAC 2021 Best Paper. The paper presents Gemmini, "an open-source, full-stack DNN accelerator generator for DNN workloads, enabling end-to-e... » read more

Advances In Reconfigurable Intelligent Surfaces Hardware Architectures: Beyond 5G/6G


This technical paper titled "Reconfigurable Intelligent Surfaces for Wireless Communications: Overview of Hardware Designs, Channel Models, and Estimation Techniques" is from researchers at IEEE. The paper's abstract states "we overview and taxonomize the latest advances in RIS [reconfigurable intelligent surfaces] hardware architectures as well as the most recent developments in the modelin... » read more

Implementing Cryptographic Algorithms for the RISC-V Instruction Set Architecture in Two Cases


This new technical paper titled "Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms" was published by researchers at Intel, North Arizona University and Google, with partial funding from U.S. Air Force Research Laboratory. Abstract "The ever-increasing need for securing computing systems using cryptographic algorithms is spurring interest in the efficient i... » read more

ISO-26262 Hardware Architecture


This new technical paper titled "Safety-Oriented System Hardware Architecture Exploration in Compliance with ISO 26262" was published by researchers at National Taipei University. Abstract "Safety-critical intelligent automotive systems require stringent dependability while the systems are in operation. Therefore, safety and reliability issues must be addressed in the development of such sa... » read more

Efficient Neuromorphic AI Chip: “NeuroRRAM”


New technical paper titled "A compute-in-memory chip based on resistive random-access memory" was published by a team of international researchers at Stanford, UCSD, University of Pittsburgh, University of Notre Dame and Tsinghua University. The paper's abstract states "by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present ... » read more

Techniques For Improving Energy Efficiency of Training/Inference for NLP Applications, Including Power Capping & Energy-Aware Scheduling


This new technical paper titled "Great Power, Great Responsibility: Recommendations for Reducing Energy for Training Language Models" is from researchers at MIT and Northeastern University. Abstract: "The energy requirements of current natural language processing models continue to grow at a rapid, unsustainable pace. Recent works highlighting this problem conclude there is an urgent need ... » read more

Formal Verification Methodology For Detecting Security-Critical Bugs in HW & in the HW/Firmware Interface of SoCs (Award Winner)


A new technical paper titled "A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level" was this year's first place winner of Intel's Hardware Security Academic Award program.   The approach utilizes UPEC (Unique Program Execution Checking) to identify functional design bugs causing confidentiality violations, covering both the processor and its peripherals. ... » read more

Using GPUs to Speed Up DFIT Analysis


Researchers at National University of Singapore and an independent researcher presented a new technical paper titled "FlowMatrix: GPU-Assisted Information-Flow Analysis through Matrix-Based Representation" at the USENIX Security Symposium in Boston in August 2022. Abstract: "Dynamic Information Flow Tracking (DIFT) forms the foundation of a wide range of security and privacy analyses. The ... » read more

An Escalation of Rowhammer To Rows Beyond Immediate Neighbors


Researchers at Graz University of Technology, Lamarr Security Research, Google, AWS, and Rivos presented this new technical paper titled "Half-Double: Hammering From the Next Row Over" at the USENIX Security Symposium in Boston in August 2022. Abstract: "Rowhammer is a vulnerability in modern DRAM where repeated accesses to one row (the aggressor) give off electrical disturbance whose cumu... » read more

Heterogenous Computing & Cache Attacks


Researchers at imec-COSIC, KU Leuven presented this paper titled "Double Trouble: Combined Heterogeneous Attacks on Non-Inclusive Cache Hierarchies" at the USENIX Security Symposium in Boston in August 2022. Note, this is a prepublication paper. Abstract: "As the performance of general-purpose processors faces diminishing improvements, computing systems are increasingly equipped with domai... » read more

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