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Optimizing Quantum Gates For Error Correction in Superconducting Qubits (Google AI)
By Technical Paper Link - 25 Mar, 2024 - Comments: 0

A new technical paper titled "Optimizing quantum gates towards the scale of logical qubits" was published by researchers at Google AI and UC Riverside. Abstract "A foundational assumption of quantum error correction theory is that quantum gates can be scaled to large processors without exceeding the error-threshold for fault tolerance. Two major challenges that could become fundamental road... » read more

HW Implementation of Memristive ANNs
By Technical Paper Link - 22 Mar, 2024 - Comments: 0

A new technical paper titled "Hardware implementation of memristor-based artificial neural networks" was published by KAUST, Universitat Autònoma de Barcelona, IBM Research, USC, University of Michigan and others. Abstract: "Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units oper... » read more

Hardware Trojans: CPU-Oriented Trojan Trigger Circuits (Georgia Tech)
By Technical Paper Link - 22 Mar, 2024 - Comments: 0

A new technical paper titled "Towards Practical Fabrication Stage Attacks Using Interrupt-Resilient Hardware Trojans" was published by researchers at Georgia Tech. The paper states: "We introduce a new class of hardware trojans called interrupt-resilient trojans (IRTs). Our work is motivated by the observation that hardware trojan attacks on CPUs, even under favorable attack scenarios (e.g.... » read more

U.S. Strategy on Microelectronics Research
By Technical Paper Link - 19 Mar, 2024 - Comments: 0

The U.S. government released a 61 page report titled "National Strategy on Microelectronics Research" by the Subcommittee On Microelectronics Leadership, Committee on Homeland and National Security of the National Science and Technology Council. The report states four goals guiding the agency's efforts in microelectronics research: "Goal 1. Enable and accelerate research advances for futu... » read more

Transformer Model Based Clustering Methodology For Standard Cell Layout Automation (Nvidia)
By Technical Paper Link - 19 Mar, 2024 - Comments: 0

A new technical paper titled "Novel Transformer Model Based Clustering Method for Standard Cell Design Automation" was published by researchers at Nvidia. Abstract "Standard cells are essential components of modern digital circuit designs. With process technologies advancing beyond 5nm, more routability issues have arisen due to the decreasing number of routing tracks (RTs), increasing numb... » read more

Quantum Computing: New Ion Trap On A Microfabricated Chip (ETH Zurich)
By Technical Paper Link - 19 Mar, 2024 - Comments: 0

A new technical paper titled "Penning micro-trap for quantum computing" was published by researchers at ETH Zürich, Leibniz Universität Hannover, and Physikalisch-Technische Bundesanstalt. Abstract "Trapped ions in radio-frequency traps are among the leading approaches for realizing quantum computers, because of high-fidelity quantum gates and long coherence times. However, the use of r... » read more

An Open Hardware Approach in Quantum Technology
By Technical Paper Link - 19 Mar, 2024 - Comments: 0

A technical paper titled "Open Hardware Solutions in Quantum Technology" was published by researchers at Unitary Fund, Qruise GmbH, Technical University of Valencia, Lawrence Berkeley National Laboratory, Fermi National Accelerator Laboratory, Sandia National Laboratories, and others. Abstract "Quantum technologies such as communications, computing, and sensing offer vast opportunities for ... » read more

Predicting Warpage in Different Types of IC Stacks At Early Stage Of Package Design
By Technical Paper Link - 15 Mar, 2024 - Comments: 0

A new technical paper titled "Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects" was published by researchers at Siemens EDA, D2S, and Univ. Grenoble Alpes, CEA, Leti. Abstract: "A physics-based multi-scale simulation methodology that analyses die stress variations generated by package fabrication is employed for warpage study. The ... » read more

Band-To-Band Tunneling And Negative Differential Resistance in Heterojunctions Built Entirely Using 2D Materials
By Technical Paper Link - 15 Mar, 2024 - Comments: 0

A technical paper titled "Electrical characterization of multi-gated WSe2 /MoS2 van der Waals heterojunctions" was published by researchers at Helmholtz-Zentrum Dresden Rossendorf (HZDR), TU Dresden, National Institute for Materials Science (Japan) and NaMLab gGmbH. Abstract "Vertical stacking of different two-dimensional (2D) materials into van der Waals heterostructures exploits the pr... » read more

TCAM-SSD: A Framework For In-SSD Associative Search Using NAND Flash Memory
By Technical Paper Link - 15 Mar, 2024 - Comments: 0

A new technical paper titled "TCAM-SSD: A Framework for Search-Based Computing in Solid-State Drives" was published by researchers at University of Illinois Urbana-Champaign, Carnegie Mellon University, Samsung Electronics and Sandia National Laboratories. Abstract "As the amount of data produced in society continues to grow at an exponential rate, modern applications are incurring signific... » read more

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