Author's Latest Posts


Performance Of A Memory System With FeRAM vs. DRAM (Georgia Tech, Imec, NTUA)


A new technical paper titled "Benchmarking of FERAM-Based Memory System by Optimizing Ferroelectric Device Model" was published by researchers at Georgia Tech, imec and National Technical University of Athens. Abstract "We present a framework for design technology co-optimization (DTCO) of the main memory system with one transistor-one capacitor (1T1C) ferroelectric random access memory (FE... » read more

AUTOSAR-Aligned Analysis Of 180 SoC Vulnerabilities In Auto Architecture (Chalmers, Univ. of Gothenburg)


A new technical paper titled "An AUTOSAR-Aligned Architectural Study of Vulnerabilities in Automotive SoC Software" was published by researchers at Chalmers University of Technology and University of Gothenburg. Abstract "Cooperative, Connected and Automated Mobility (CCAM) are complex cyber-physical systems (CPS) that integrate computation, communication, and control in safety-critical env... » read more

An Overview Of Recent Progress On The EUV + DSA Strategy (Univ. of Chicago, Berkeley Lab, Argonne)


A new technical paper titled "Directed self-assembly of block copolymers for high-precision patterning in the era of extreme ultraviolet lithography" was published by researchers at University of Chicago, Lawrence Berkeley National Laboratory and Argonne National Laboratory. Abstract "Extreme ultraviolet (EUV) lithography enables unprecedented resolution in semiconductor patterning but face... » read more

Multimodal LLM Assistant for Chip Physical Design (National Taiwan Univ., UCLA, NVIDIA)


A new technical paper titled "Multimodal Chip Physical Design Engineer Assistant" was published by researchers at National Taiwan University, University of California, Los Angeles and NVIDIA Research. Abstract "Modern chip physical design relies heavily on Electronic Design Automation (EDA) tools, which often struggle to provide interpretable feedback or actionable guidance for improving ro... » read more

Six-Stack Vertically Integrated Hybrid Platform For Large Area Electronics (KAUST, Imperial College Et Al.)


A new technical paper titled "Three-dimensional integrated hybrid complementary circuits for large-area electronics" was published by researchers at KAUST, Imperial College London and the University of Manchester. Abstract "The development of low-power computing sectors requires compact, power-efficient and high-performance integrated circuits. Hybrid technology that combines n-type metal o... » read more

Thermal Simulation And Optimization in 3D-IC Design (Intel, UCSB, Cadence)


A new technical paper titled "DeepOHeat-v1: Efficient Operator Learning for Fast and Trustworthy Thermal Simulation and Optimization in 3D-IC Design" was published by researchers at Intel Corporation, University of California, Santa Barbara and Cadence. Abstract "Thermal analysis is crucial in 3D-IC design due to increased power density and complex heat dissipation paths. Although operator ... » read more

Photonics as a Carbon-Sustainable Solution for Next-Gen AI Hardware (Boston Univ., NY CREATES, Lightmatter, Cornell Tech)


A new technical paper titled "Photonics for sustainable AI" was published by researchers at Boston University, NY CREATES, Lightmatter and Cornell Tech. Abstract "The rising computational demands of Artificial Intelligence (AI) are driving a rapid surge in carbon emissions from the Information and Communications Technology (ICT) sector. Traditional CMOS-based computing is reaching its scali... » read more

Implementing Power Dynamic Response For Greener AI Data Centers (Univ. of Cambridge, Nyobolt, Nanyang Tech)


A new technical paper titled "Improving AI Efficiency in Data Centres by Power Dynamic Response" was published by researchers at University of Cambridge, Nyobolt Limited and Nanyang Technological University. Abstract "The steady growth of artificial intelligence (AI) has accelerated in the recent years, facilitated by the development of sophisticated models such as large language models and... » read more

Modulation of the Inner Gate Length in MFMIS NSFETs To Achieve Big Gains in Memory Window (Samsung, Seoul National Univ.)


A new technical paper titled "Inner Gate Length Modulation of MFMIS Nanosheet FET Memory for Advanced Technology Nodes" was published by researchers at Samsung and Seoul National University. Abstract "This work proposes a new way of lowering the area ratio (AR) between the ferroelectric and metal-oxide-semiconductor (MOS) regions of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) ... » read more

Understanding and Mitigating Column-Based Read Disturbance in DRAM Chips (ETH Zurich, CISPA)


A new technical paper titled "ColumnDisturb: Understanding Column-based Read Disturbance in Real DRAM Chips and Implications for Future Systems" was published by researchers at ETH Zurich and CISPA. Abstract "We experimentally demonstrate a new widespread read disturbance phenomenon, ColumnDisturb, in real commodity DRAM chips. By repeatedly opening or keeping a DRAM row (aggressor row) ope... » read more

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