Author's Latest Posts

Intelligence Per Watt: Measuring Local Inference Viability, Studying 20+ Models, 8 HW Accelerators (Stanford Univ.)
By Technical Paper Link - 18 Nov, 2025 - Comments: 0

A new technical paper titled "Intelligence per Watt: Measuring Intelligence Efficiency of Local AI" was published by researchers at Stanford University and Together AI. Abstract: "Large language model (LLM) queries are predominantly processed by frontier models in centralized cloud infrastructure. Rapidly growing demand strains this paradigm, and cloud providers struggle to scale infrastruc... » read more

Edge AI Safety: Agentic AI Architecture That Leverages 3D To Integrate A Dedicated Safety Layer (Princeton, HKUST, NC State Univ.)
By Technical Paper Link - 17 Nov, 2025 - Comments: 0

A new technical paper titled "3D Guard-Layer: An Integrated Agentic AI Safety System for Edge Artificial Intelligence" was published by researchers at Princeton University, Hong Kong University of Science and Technology, and North Carolina State University. Abstract "AI systems have found a wide range of real-world applications in recent years. The adoption of edge artificial intelligence, ... » read more

Mitigating Structural Defects During The Growth Of 2D vdW Chalcogenides By MBE (Penn State Univ.)
By Technical Paper Link - 17 Nov, 2025 - Comments: 0

A new technical paper titled "Mitigation of Structural Defects during the Growth of 2D van der Waals Chalcogenides by Molecular Beam Epitaxy" was published by researchers at Penn State University. Abstract "The growth of wafer-scale van der Waals (vdW) thin films and heterostructures by molecular beam epitaxy (MBE) is important for future applications in quantum technologies, next-generatio... » read more

New Interconnect Materials Beyond Copper (Florida State Univ., Cornell)
By Technical Paper Link - 14 Nov, 2025 - Comments: 0

A new technical paper titled "Shrinking interconnects beyond copper" was published by researchers at Florida State University and Cornell University. Excerpt "The continuous downscaling of transistors in integrated circuits following Moore’s law—doubling the number of transistors on a microchip about every 2 years—has been an extraordinary feat of engineering, pushing the limits of fu... » read more

Comparative Analysis of CFET and NSFET Architectures (TU Munich, IIT)
By Technical Paper Link - 14 Nov, 2025 - Comments: 0

A new technical paper titled "Impact of Aging, Self-Heating, and Parasitics Effects on NSFET and CFET" was published by researchers at TU Munich and Indian Institute of Technology. Abstract "This work presents a comparative analysis of complementary field-effect transistor (CFET) and nanosheet FET (NSFET) architectures, with a focus on self-heating effects (SHEs), negative bias temperature ... » read more

Parallel Implementation Of Nonlinear Functions Using An Optical Processor (UCLA)
By Technical Paper Link - 12 Nov, 2025 - Comments: 0

A new technical paper titled "Massively parallel and universal approximation of nonlinear functions using diffractive processors" was published by researchers at UCLA. Abstract "Nonlinear computation is essential for a wide range of information processing tasks, yet implementing nonlinear functions using optical systems remains a challenge due to the weak and power-intensive nature of optic... » read more

Interplay Between the Row Hammer Effect and Floating Body Effect in Monolithic 3D Stackable 1T1C DRAM (Georgia Tech)
By Technical Paper Link - 11 Nov, 2025 - Comments: 0

A new technical paper titled "Row Hammer Effect and Floating Body Effect of Monolithic 3D Stackable 1T1C DRAM" was published by researchers at Georgia Institute of Technology. Abstract "Monolithic 3D stackable 1T1C DRAM technology is on the rise, with initial prototypes reported by the industry. This work presents a comprehensive reliability study focusing on the intricate interplay between... » read more

3D Imaging Buried Interfaces In Twisted Oxide Moirés (Cornell, SLAC, Stanford et al.)
By Technical Paper Link - 11 Nov, 2025 - Comments: 0

A new technical paper titled "Mind the Gap -- Imaging Buried Interfaces in Twisted Oxide Moirés" was published by researchers at Cornell University, SLAC National Accelerator Laboratory, Stanford University, USC, North Carolina State University, University of Chicago, Institute for Basic Science and POSTECH. Abstract "The ability to tune electronic structure in twisted stacks of layered, t... » read more

Silicon Photonic Interconnected Chiplets With Computational Network And IMC For LLM Inference Acceleration (NUS)
By Technical Paper Link - 10 Nov, 2025 - Comments: 0

A new technical paper titled "PICNIC: Silicon Photonic Interconnected Chiplets with Computational Network and In-memory Computing for LLM Inference Acceleration" was published by researchers at the National University of Singapore. Abstract "This paper presents a 3D-stacked chiplets based large language model (LLM) inference accelerator, consisting of non-volatile in-memory-computing proces... » read more

Free-Space Gated Transistor In Wide Bandgap And Ultra Wide Bandgap Semiconductors (KAUST Et Al.)
By Technical Paper Link - 10 Nov, 2025 - Comments: 0

A new technical paper titled "Lateral Semiconductor–Free-Space Gate Transistors" was published by researchers at KAUST and the Indian Institute of Technology. Abstract "We introduce a novel lateral transistor architecture, the semiconductor−free-space gate transistor (SFGT), in which the conventional solid dielectric is replaced by a semiconductor−free-space gate configuration with su... » read more

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