Author's Latest Posts


Co-Optimizing GPU Architecture And SW To Enhance Edge Inference Performance (NVIDIA)


A new technical paper titled "EdgeReasoning: Characterizing Reasoning LLM Deployment on Edge GPUs" was published by researchers at NVIDIA. Abstract "Edge intelligence paradigm is increasingly demanded by the emerging autonomous systems, such as robotics. Beyond ensuring privacy-preserving operation and resilience in connectivity-limited environments, edge deployment offers significant energ... » read more

Blend Strategy To Improve Edge Resistance Capability And Thickness Of EUV-Fabricated Nanopatterns (National Tsing Hua Univ.)


A new technical paper titled "Enhanced Edge Etching Resistance and EUV Lithographic Performance of a Tin-Oxide Photoresist via a Blend Strategy" was published by researchers at National Tsing Hua University. Abstract "Enhancing the edge resistance capability of extensively studied metal carboxylate clusters as extreme ultraviolet (EUV) photoresists is a formidable and unsolved task. This wo... » read more

Overcoming The vdW Gap Bottleneck in Semiconductor Scaling (TU Wien)


A new technical paper titled "The van der Waals Gap: a Hidden Showstopper in Semiconductor Device Scaling" was published by researchers at TU Wien. Abstract "Continued miniaturization of transistors is critical for sustaining advances in computing performance, energy efficiency, and integration density. A central nanoscale challenge is controlling gate leakage through ultrathin dielectrics.... » read more

Three-Terminal Memtransistors for Decentralized Edge Applications (Penn State, NIWC)


A new technical paper titled "Large-scale crossbar arrays based on three-terminal MoS2 memtransistors" was published by researchers at Penn State University and Naval Information Warfare Center Pacific. Abstract "Memristive crossbar architectures are promising as efficient, low-power inference engines for edge AI applications. However, inputs with minor differences often yield similar outpu... » read more

Co-Simulation Framework for Parallel DNN Execution on Chiplet-Based Systems (UW–Madison, Washington State)


A new technical paper titled "CHIPSIM: A Co-Simulation Framework for Deep Learning on Chiplet-Based Systems" was published by researchers at University of Wisconsin–Madison and Washington State University. Abstract "Due to reduced manufacturing yields, traditional monolithic chips cannot keep up with the compute, memory, and communication demands of data-intensive applications, such as ra... » read more

Emergence Of The JJFET For Cryogenic and Quantum-Compatible Logic (Univ. of Glasgow)


A new technical paper titled "Silicon-based Josephson junction field-effect transistors enabling cryogenic logic and quantum technologies" was published by researchers at University of Glasgow. Abstract "The continuous miniaturisation of metal-oxide-semiconductor field-effect transistors (MOSFETs) from long- to short-channel architectures has advanced beyond the predictions of Moore's Law. ... » read more

MIT’s Survey On Accelerators and Processors for Inference, With Peak Performance And Power Comparisons


A new technical paper titled "Lincoln AI Computing Survey (LAICS) and Trends" was published by researchers at MIT Lincoln Laboratory Supercomputing Center. Abstract "In the past year, generative AI (GenAI) models have received a tremendous amount of attention, which in turn has increased attention to computing systems for training and inference for GenAI. Hence, an update to this survey is ... » read more

SOT-Based MRAM Design At 7nm (Georgia Tech, Intel)


A new technical paper titled "Comprehensive device to system co-design for SOT-MRAM at the 7nm node" was published by researchers at Georgia Institute of Technology and Intel. Abstract "This work presents a comprehensive spin-orbit torque (SOT) based random access memory (MRAM) design at the 7nm technology node, spanning from device-level characteristics to system-level power performance ar... » read more

In-DRAM TRNG Using Simultaneous Multiple-Row Activation (ETH Zurich, CISPA)


A new technical paper titled "In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips" was published by researchers at ETH Zürich and CISPA. Abstract "In this work, we experimentally demonstrate that it is possible to generate true random numbers at high throughput and low latency in commercial off-the-shelf (COTS) DRAM chi... » read more

Utilizing Chiplet-Locality For Efficient Memory Mapping In MCM GPUs (ETRI, Sungkyunkwan Univ.)


A new technical paper titled "Leveraging Chiplet-Locality for Efficient Memory Mapping in Multi-Chip Module GPUs" was published by researchers at Electronics and Telecommunications Research Institute (ETRI) and Sungkyunkwan University. Abstract "While the multi-chip module (MCM) design allows GPUs to scale compute and memory capabilities through multi-chip integration, it introduces memory ... » read more

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