A new technical paper titled “Lateral Semiconductor–Free-Space Gate Transistors” was published by researchers at KAUST and the Indian Institute of Technology.
Abstract
“We introduce a novel lateral transistor architecture, the semiconductor−free-space gate transistor (SFGT), in which the conventional solid dielectric is replaced by a semiconductor−free-space gate configuration with sub-100 nm fin channels and dual side gates. This work presents the first demonstration of free-space gating in wide and ultrawide bandgap semiconductors, achieving performance on par with oxide-gated transistors. SFGTs fabricated using β-Ga2O3 exhibit subthreshold slopes below 200 mV/dec, high drain current exceeding 250 mA/mm, hysteresis under 230 mV, ION/IOFF ratios above 106, and breakdown voltages over 500 V. The absence of a solid dielectric layer, combined with the open gate geometry, enables direct access to the gate region for external electric field modulation and threshold voltage tuning, while mitigating the detrimental effects of charges and trap states in conventional dielectrics. These results show the potential of SFGTs for future memory, sensing, and power applications.”
Find the technical paper here. October 2025.
García, Glen Isaac Maciel, Vishal Khandelwal, Ganesh Mainali, Víctor Dorantes Paulín, Biplab Sarkar, and Xiaohang Li. “Lateral Semiconductor–Free-Space Gate Transistors.” Nano Letters 25, no. 43 (2025): 15579. Creative commons license.
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