Author's Latest Posts


Uncovering A Significant Residual Attack Surface For Cross-Privilege Spectre-V2 Attacks


A technical paper titled “InSpectre Gadget: Inspecting the Residual Attack Surface of Cross-privilege Spectre v2” was presented at the August 2024 USENIX Security Symposium by researchers at Vrije Universiteit Amsterdam. Abstract: "Spectre v2 is one of the most severe transient execution vulnerabilities, as it allows an unprivileged attacker to lure a privileged (e.g., kernel) victim into... » read more

Data Memory-Dependent Prefetchers Pose SW Security Threat By Breaking Cryptographic Implementations


A technical paper titled “GoFetch: Breaking Constant-Time Cryptographic Implementations Using Data Memory-Dependent Prefetchers” was presented at the August 2024 USENIX Security Symposium by researchers at University of Illinois Urbana-Champaign, University of Texas at Austin, Georgia Institute of Technology, University of California Berkeley, University of Washington, and Carnegie Mellon U... » read more

A New Low-Cost HW-Counterbased RowHammer Mitigation Technique


A technical paper titled “ABACuS: All-Bank Activation Counters for Scalable and Low Overhead RowHammer Mitigation” was presented at the August 2024 USENIX Security Symposium by researchers at ETH Zurich. Abstract: "We introduce ABACuS, a new low-cost hardware-counterbased RowHammer mitigation technique that performance-, energy-, and area-efficiently scales with worsening Ro... » read more

5 Novel Layout Design Methodologies For The 3nm Nanosheet FET Library (Samsung, KNU)


A new technical paper titled "Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node" was published by researchers at Samsung Electronics and Kyungpook National University (KNU). Abstract: "As the technology nodes approach 3 nm and beyond, nanosheet FETs (NSFETs) are replacing FinFETs. However, despite the migration of devices ... » read more

The Impact Of Simulation On The Carbon Footprint of Wafer Fab Equipment R&D


A new technical paper titled "Achieving Sustainability in the Semiconductor Industry: The Impact of Simulation and AI" was published by researchers at Lam Research. Abstract "Computational simulation has been used in the semiconductor industry since the 1950s to provide engineers and managers with a faster, more cost-effective method of designing semiconductors. With increased pressure in t... » read more

Potential Of 2D Semi-Metallic PtSe2 As Source/Drain Contacts For 2D Material FETs


A technical paper titled “Improvement of Contact Resistance and 3D Integration of 2D Material Field-Effect Transistors Using Semi-Metallic PtSe2 Contacts” was published by researchers at Yonsei University, Korea Advanced Institute of Science and Technology (KAIST), Lincoln University College, Korea Institute of Science and Technology (KIST), and Ewha Womans University. Abstract: "In this ... » read more

Freeing Up Near-Memory Capacity For Cache Using Compression Techniques In A Flat Hybrid-Memory Architecture


A technical paper titled “HMComp: Extending Near-Memory Capacity using Compression in Hybrid Memory” was published by researchers at Chalmers University of Technology and ZeroPoint Technologies. Abstract: "Hybrid memories, especially combining a first-tier near memory using High-Bandwidth Memory (HBM) and a second-tier far memory using DRAM, can realize a large and low cost, high-bandwi... » read more

Electrochemical RAM Cross-Point Arrays For An Analog DL Accelerator


A technical paper titled “Retention-aware zero-shifting technique for Tiki-Taka algorithm-based analog deep learning accelerator” was published by researchers at Pohang University of Science and Technology, Korea University, and Kyungpook National University. "We present the fabrication of 4 K-scale electrochemical random-access memory (ECRAM) cross-point arrays for analog neural network... » read more

Data Filtering Directly Within A NAND Flash Memory Chip


A technical paper titled “Search-in-Memory (SiM): Reliable, Versatile, and Efficient Data Matching in SSD's NAND Flash Memory Chip for Data Indexing Acceleration” was published by researchers at TU Dortmund, Academia Sinica, and National Taiwan University. "This paper introduces the Search-in-Memory (SiM) chip, which demonstrates the feasibility of performing data filtering directly with... » read more

Dual Graphite-Gated BLG As Platform for Cryogenic FETs


A technical paper titled “Ultra-steep slope cryogenic FETs based on bilayer graphene” was published by researchers at RWTH Aachen University, Forschungszentrum Julich, National Institute for Materials Science (Japan), and AMO GmbH. "Here, we show that FETs based on Bernal stacked bilayer graphene encapsulated in hexagonal boron nitride and graphite gates exhibit inverse subthreshold slop... » read more

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