Author's Latest Posts


Cross-Node Scaling Potential of SOT-MRAM for Last-Level Caches (imec)


A new technical paper titled "SOT-MRAM Bitcell Scaling with BEOL Read Selectors: A DTCO Study" was published by researchers at imec, Leuven, and 3001 Belgium. Abstract "This work explores the cross-node scaling potential of SOT-MRAM for last-level caches (LLCs) under heterogeneous system scaling paradigm. We perform extensive Design-Technology Co-Optimization (DTCO) exercises to evaluate th... » read more

Operational Cybersecurity and Supply Chain Risks Across the AI Lifecycle (Sandia National Labs)


A new technical paper titled "Surveying the Operational Cybersecurity and Supply Chain Threat Landscape when Developing and Deploying AI Systems" was published by researchers at Sandia National Labs. Abstract "The rise of AI has transformed the software and hardware landscape, enabling powerful capabilities through specialized infrastructures, large-scale data storage, and advanced hardware... » read more

2025 Critical Hardware Weaknesses (Hardware CWE Special Interest Group)


A new technical paper titled "2025 Most Important Hardware Weaknesses" was published by researchers at Hardware CWE Special Interest Group. Excerpt "The Most Important Hardware Weaknesses (MIHW) empowers organizations with the knowledge to proactively strengthen hardware security and reduce risks at the source. The 2025 CWE MIHW represents a refreshed and enhanced effort to identify and edu... » read more

Electrochemical Absorption of Hydrogen in Structured Palladium Thin-Film Electrodes (Univ. of Bristol)


A new technical paper titled "Exploring Electrochemical Methods for Precision Stress Control in Nanoscale Devices " was published by researchers at the University of Bristol. Abstract "Tuning the local film stress (and associated strain) provides a universal route toward exerting dynamic control on propagating fields in nanoscale geometries and engineering controlled interactions between th... » read more

LLM-Based Chiplet Design Generation Framework (Univ. of Minnesota)


A new technical paper titled "MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging" was published by researchers at the University of Minnesota - Twin Cities. Abstract "As program workloads (e.g., AI) increase in size and algorithmic complexity, the primary challenge lies in their high dimensionality, encompassing computing cores, array sizes, and memory hierarch... » read more

Dynamic KV Cache Scheduling in Heterogeneous Memory Systems for LLM Inference (Rensselaer Polytechnic Institute, IBM)


A new technical paper titled "Accelerating LLM Inference via Dynamic KV Cache Placement in Heterogeneous Memory System" was published by researchers at Rensselaer Polytechnic Institute and IBM. Abstract "Large Language Model (LLM) inference is increasingly constrained by memory bandwidth, with frequent access to the key-value (KV) cache dominating data movement. While attention sparsity red... » read more

Power Stabilization To Allow Continued Scaling Of AI Training Workloads (Microsoft, OpenAI, NVIDIA)


A new technical paper titled "Power Stabilization for AI Training Datacenters" was published by researchers at Microsoft, OpenAI, and NVIDIA. Abstract "Large Artificial Intelligence (AI) training workloads spanning several tens of thousands of GPUs present unique power management challenges. These arise due to the high variability in power consumption during the training. Given the synchron... » read more

A Comparative Study With Horizontal and Verticals FETs (POSTECH, Georgia Tech)


A new technical paper titled "Vertical FET Optimization at Angstrom Nodes: A Comparative Study With Horizontal FET" was published by researchers at POSTECH and Georgia Institute of Technology. Abstract "For the first time, this study presents two novel vertical FET (VFET) structures and conducts a quantitative analysis to assess the competitiveness of VFET in comparison to two types of hori... » read more

An LLM-based Agentic Framework For Photonic IC Design Automation (U. of Toronto, Max Planck, MIT Et Al.)


A new technical paper titled "AI Agents for Photonic Integrated Circuit Design Automation" was published by researchers at the University of Toronto, Max Planck Institute of Microstructure Physics, GDSFactory, MIT and Axiomatic_AI Inc. Abstract "We present Photonics Intelligent Design and Optimization (PhIDO), a multi-agent framework that converts natural-language photonic integrated circui... » read more

Hardware Technologies And Algorithms for Vector Symbolic Architectures (Purdue Univ., Georgia Tech)


A new technical paper titled "Cross-Layer Design of Vector-Symbolic Computing: Bridging Cognition and Brain-Inspired Hardware Acceleration" was published by researchers at Purdue University and Georgia Institute of Technology. Abstract "Vector Symbolic Architectures (VSAs) have been widely deployed in various cognitive applications due to their simple and efficient operations. The widesprea... » read more

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