Author's Latest Posts


Integrating Digital Twins on Automotive Standardized Architectures (McMaster University)


A new technical paper titled "Engineering Automotive Digital Twins on Standardized Architectures: A Case Study" was published by researchers at McMaster Centre for Software Certification and McMaster University. Abstract "Digital twin (DT) technology has become of interest in the automotive industry. There is a growing need for smarter services that utilize the unique capabilities of DTs, r... » read more

3D-Stacked HBM Architecture Susceptibility To Thermal Attacks (NC A&T State, New Mexico State)


A new technical paper titled "On the Thermal Vulnerability of 3D-Stacked High-Bandwidth Memory Architectures" was published by researchers at North Carolina A&T State University and New Mexico State University. Abstract "3D-stacked High Bandwidth Memory (HBM) architectures provide high-performance memory interactions to address the well-known performance challenge, namely the memory wal... » read more

Optimizing LLM Training Under GPU Memory Constraints (Argonne, RIT)


A new technical paper titled "MLP-Offload: Multi-Level, Multi-Path Offloading for LLM Pre-training to Break the GPU Memory Wall" was published by researchers at Argonne National Laboratory and Rochester Institute of Technology. Abstract "Training LLMs larger than the aggregated memory of multiple GPUs is increasingly necessary due to the faster growth of LLM sizes compared to GPU memory. To... » read more

A Fundamental Rethinking Of Memory Hierarchy Design (Stanford University)


A new technical paper titled "The Future of Memory: Limits and Opportunities" was published by researchers at Stanford University and an independent researcher. Abstract "Memory latency, bandwidth, capacity, and energy increasingly limit performance. In this paper, we reconsider proposed system architectures that consist of huge (many-terabyte to petabyte scale) memories shared among large ... » read more

HW Security: 2.5D and 3D Technologies Provide Opportunities in Designing Secure Systems (UCSB, Columbia)


A new technical paper titled "Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges" was published by researchers at the University of California, Santa Barbara and Columbia University. Abstract "3D die stacking and 2.5D interposer design are promising technologies to improve integration density, performance and cost. Current approaches face serious issues in dealin... » read more

Overview of Incorporating LLMs into EDA, With 3 Case Studies (TU Munich et al.)


A new technical paper titled "Large Language Models (LLMs) for Electronic Design Automation (EDA)" was published by researchers at the Technical University of Munich, University of Stuttgart, New York University, and University of Siegen. Abstract "With the growing complexity of modern integrated circuits, hardware engineers are required to devote more effort to the full design-to-manufactu... » read more

Simulating HW with C Speed and RTL Accuracy for HLS Designs (Georgia Tech)


A new technical paper titled "OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs" was published by researchers at Georgia Institute of Technology. Abstract "High-Level Synthesis (HLS) is increasingly popular for hardware design using C/C++ instead of Register-Transfer Level (RTL). To express concurrent hardware behavior in a sequential language like ... » read more

Heterogeneous Multi-Core Architecture Optimizing Power Consumption (TU Dresden)


A new technical paper titled "Balancing Power and Performance With Task Dependencies in Multi-Core Systems" was published by researchers at TU Dresden. Abstract "The increasing use of FPGAs necessitates energy-efficient solutions, particularly for battery-powered applications. Although power dissipation is often perceived as a hardware issue, it can be mitigated through power-saving techniq... » read more

Tools, Models and System Support for PIM Architectures, With DRAM-Focus (ETH Zurich)


A new technical paper titled "New Tools, Programming Models, and System Support for Processing-in-Memory Architectures" was published by researchers at ETH Zurich. Abstract "Our goal in this dissertation is to provide tools, programming models, and system support for PIM architectures (with a focus on DRAM-based solutions), to ease the adoption of PIM in current and future systems. To this ... » read more

Wafer-Scale Heterogeneous Integration of Lithium Tantalate Films on Low-Loss Silicon Nitride Photonic ICs (EPFL, KIT, CAS, IPQ)


A new technical paper titled "Heterogeneously integrated lithium tantalate-on-silicon nitride modulators for high-speed communications" was published by researchers at EPFL, Chinese Academy of Sciences, IPQ and KIT. Abstract "Driven by the prospects of higher bandwidths for optical interconnects, integrated modulators involving materials beyond those available in silicon manufacturing incre... » read more

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