Author's Latest Posts

Double Duty Logic Block Architecture Enabling Concurrent LUT and Adder Chain Usage (Nanyang Technological Univ. et al)
By Technical Paper Link - 02 Oct, 2025 - Comments: 0

A new technical paper titled "Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage" was published by researchers at Nanyang Technological University, Cornell University, Altera, University of Waterloo and University of Toronto. Abstract "Flexibility and customization are key strengths of Field-Programmable Gate Arrays (FPGAs) when compared to other computing devices... » read more

Performance And Energy Characterization Of A Commercial Compute-in-SRAM Device (Cornell, USC, MIT, GSI)
By Technical Paper Link - 16 Sep, 2025 - Comments: 0

A new technical paper titled "Characterizing and Optimizing Realistic Workloads on a Commercial Compute-in-SRAM Device" was published by researchers at Cornell University, USC, MIT and GSI Technology Inc. Abstract "Compute-in-SRAM architectures offer a promising approach to achieving higher performance and energy efficiency across a range of data-intensive applications. However, prior evalu... » read more

Cost-Effective, Orthogonal Approach to Resilient Memory Design (Univ. of Central Florida, UT San Antonio, Rochester)
By Technical Paper Link - 16 Sep, 2025 - Comments: 0

A new technical paper titled "SCREME: A Scalable Framework for Resilient Memory Design" was published by researchers at University of Central Florida, University of Texas at San Antonio and University of Rochester. Abstract "The continuing advancement of memory technology has not only fueled a surge in performance, but also substantially exacerbate reliability challenges. Traditional soluti... » read more

HW/SW Co-Design to Retarget the Compiler For RISC-V Custom Instructions (Tampere Univ.)
By Technical Paper Link - 16 Sep, 2025 - Comments: 0

A new technical paper titled "Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions" was published by researchers at Tampere University. Abstract "Custom instruction (CI) set extensions are beneficial for increasing performance and energy efficiency in a set of target applications. For rapid prototyping of these types of application-specific processors, desig... » read more

KAN Acceleration: Algorithm Hardware Co-Design Approach (Georgia Tech, National Tsing Hua Univ., TSMC)
By Technical Paper Link - 16 Sep, 2025 - Comments: 0

A new technical paper titled "Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems" was published by researchers at Georgia Institute of Technology, National Tsing Hua University and TSMC. Abstract "Recent developments have introduced Kolmogorov-Arnold Networks (KAN), an innovative architectural paradigm capable of replicating conventional deep neural network (DNN... » read more

HW-SW Co-Designed System With 3 Core Optimization Pathways For Long-Context Agentic LLM Inference (Cambridge, ICL)
By Technical Paper Link - 15 Sep, 2025 - Comments: 0

A new technical paper titled "Combating the Memory Walls: Optimization Pathways for Long-Context Agentic LLM Inference" was published by researchers at University of Cambridge, Imperial College London and University of Edinburgh. Abstract "LLMs now form the backbone of AI agents for a diverse array of applications, including tool use, command-line agents, and web or computer use agents. The... » read more

Identifying Divergences in HW Designs For High Performance Computing Workloads (LBNL et al.)
By Technical Paper Link - 15 Sep, 2025 - Comments: 0

A new technical paper titled "Towards An Approach to Identify Divergences in Hardware Designs for HPC Workloads" was published by Lawrence Berkeley National Lab (LBNL), Foundation for Research and Technology - Hellas and University of Houston Clear Lake. Abstract "Developing efficient hardware accelerators for mathematical kernels used in scientific applications and machine learning has tra... » read more

Analog IMC Attention Mechanism For Fast And Energy-Efficient LLMs (FZJ, RWTH Aachen)
By Technical Paper Link - 15 Sep, 2025 - Comments: 0

A new technical paper titled "Analog in-memory computing attention mechanism for fast and energy-efficient large language models" was published by researchers at Forschungszentrum Jülich and RWTH Aachen. Abstract "Transformer networks, driven by self-attention, are central to large language models. In generative transformers, self-attention uses cache memory to store token projec... » read more

Undervolting Attack That Exploits The Vulnerability Of Chips During Brownout Conditions (Worcester Polytechnic, RUB)
By Technical Paper Link - 15 Sep, 2025 - Comments: 0

A new technical paper titled "Chypnosis: Stealthy Secret Extraction using Undervolting-based Static Side-channel Attacks" was published by researcher at Worcester Polytechnic Institute and Ruhr University Bochum. Abstract: "Static side-channel analysis attacks, which rely on a stopped clock to extract sensitive information, pose a growing threat to embedded systems' security. To protect a... » read more

Analog Plus 3D Optics to Accelerate AI inference and Combinatorial Optimization (Microsoft, Cambridge)
By Technical Paper Link - 12 Sep, 2025 - Comments: 0

A new technical paper titled "Analog optical computer for AI inference and combinatorial optimization" was published by researchers at Microsoft Research, Barclays and University of Cambridge. Abstract "Artificial intelligence (AI) and combinatorial optimization drive applications across science and industry, but their increasing energy demands challenge the sustainability of digital comput... » read more

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