Author's Latest Posts


HW/SW Co-Design to Retarget the Compiler For RISC-V Custom Instructions (Tampere Univ.)


A new technical paper titled "Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions" was published by researchers at Tampere University. Abstract "Custom instruction (CI) set extensions are beneficial for increasing performance and energy efficiency in a set of target applications. For rapid prototyping of these types of application-specific processors, desig... » read more

KAN Acceleration: Algorithm Hardware Co-Design Approach (Georgia Tech, National Tsing Hua Univ., TSMC)


A new technical paper titled "Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems" was published by researchers at Georgia Institute of Technology, National Tsing Hua University and TSMC. Abstract "Recent developments have introduced Kolmogorov-Arnold Networks (KAN), an innovative architectural paradigm capable of replicating conventional deep neural network (DNN... » read more

HW-SW Co-Designed System With 3 Core Optimization Pathways For Long-Context Agentic LLM Inference (Cambridge, ICL)


A new technical paper titled "Combating the Memory Walls: Optimization Pathways for Long-Context Agentic LLM Inference" was published by researchers at University of Cambridge, Imperial College London and University of Edinburgh. Abstract "LLMs now form the backbone of AI agents for a diverse array of applications, including tool use, command-line agents, and web or computer use agents. The... » read more

Identifying Divergences in HW Designs For High Performance Computing Workloads (LBNL et al.)


A new technical paper titled "Towards An Approach to Identify Divergences in Hardware Designs for HPC Workloads" was published by Lawrence Berkeley National Lab (LBNL), Foundation for Research and Technology - Hellas and University of Houston Clear Lake. Abstract "Developing efficient hardware accelerators for mathematical kernels used in scientific applications and machine learning has tra... » read more

Analog IMC Attention Mechanism For Fast And Energy-Efficient LLMs (FZJ, RWTH Aachen)


A new technical paper titled "Analog in-memory computing attention mechanism for fast and energy-efficient large language models" was published by researchers at Forschungszentrum Jülich and RWTH Aachen. Abstract "Transformer networks, driven by self-attention, are central to large language models. In generative transformers, self-attention uses cache memory to store token projec... » read more

Undervolting Attack That Exploits The Vulnerability Of Chips During Brownout Conditions (Worcester Polytechnic, RUB)


A new technical paper titled "Chypnosis: Stealthy Secret Extraction using Undervolting-based Static Side-channel Attacks" was published by researcher at Worcester Polytechnic Institute and Ruhr University Bochum. Abstract: "Static side-channel analysis attacks, which rely on a stopped clock to extract sensitive information, pose a growing threat to embedded systems' security. To protect a... » read more

Analog Plus 3D Optics to Accelerate AI inference and Combinatorial Optimization (Microsoft, Cambridge)


A new technical paper titled "Analog optical computer for AI inference and combinatorial optimization" was published by researchers at Microsoft Research, Barclays and University of Cambridge. Abstract "Artificial intelligence (AI) and combinatorial optimization drive applications across science and industry, but their increasing energy demands challenge the sustainability of digital comput... » read more

Neuromorphic Computing: Memristor Based On Vertically Aligned Nanocomposite With Highly Defective Vertical Channels (Purdue, UT Arlington)


A new technical paper titled "An Ultra-Robust Memristor Based on Vertically Aligned Nanocomposite with Highly Defective Vertical Channels for Neuromorphic Computing" was published by researchers at Purdue University and University of Texas at Arlington. "In this work, a memristor based on SrTiO3-CeO2 (S-C) VAN thin films with highly defective vertical interfaces has been successfully demonst... » read more

Compromising Spectre v2 HW Mitigations By Exploiting BPRC (ETH Zurich)


A new technical paper titled "Branch Privilege Injection: Compromising Spectre v2 Hardware Mitigations by Exploiting Branch Predictor Race Conditions" was published by researchers at ETH Zurich. Presented at USENIX Security Symposium in August 2025. Abstract "Modern branch predictors prevent Spectre v2 attacks by associating predictions with the privilege domain they should be restricted to... » read more

Critical Challenges and Opportunities Related to Polymer-Based Materials in Semiconductor Packaging (NIST, NC State, NREL et al)


A new technical paper titled "Material Needs and Measurement Challenges for Advanced Semiconductor Packaging: Understanding the Soft Side of Science" was published by researchers at the National Institute of Standards and Technology, North Carolina State University, National Renewable Energy Laboratory, ASE, Intel, Innocentrix, and Binghamton University. Abstract "This Perspective builds up... » read more

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