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Ferroelectric Tunnel Junctions In Crossbar Array Analog In-Memory Compute Accelerators
By Technical Paper Link - 11 Jan, 2024 - Comments: 0

A technical paper titled “Ferroelectric Tunnel Junction Memristors for In-Memory Computing Accelerators” was published by researchers at Lund University. Abstract: "Neuromorphic computing has seen great interest as leaps in artificial intelligence (AI) applications have exposed limitations due to heavy memory access, with the von Neumann computing architecture. The parallel in-memory comp... » read more

A Potentially CMOS Compatible Integration Of Reconfigurable FETs Based On Al-Si-Al Heterostructure Sheets
By Technical Paper Link - 11 Jan, 2024 - Comments: 0

A technical paper titled “Reconfigurable Si Field-Effect Transistors With Symmetric On-States Enabling Adaptive Complementary and Combinational Logic” was published by researchers at TU Vienna and Swiss Federal Laboratories for Materials Science and Technology. Abstract: "Reconfigurable field-effect transistors (RFETs), combining n-and p-type operation in a single device, have already sho... » read more

The 40-Million-Core Sunway Supercomputer: 5 ExaFlop/s HPL-MxP Benchmark With Linear Scalability
By Technical Paper Link - 11 Jan, 2024 - Comments: 0

A technical paper titled “5 ExaFlop/s HPL-MxP Benchmark with Linear Scalability on the 40-Million-Core Sunway Supercomputer” was published by researchers at the National Research Center of Parallel Computer Engineering and Technology and Tsinghua University. Abstract: "HPL-MxP is an emerging high performance benchmark used to measure the mixed-precision computing capability of leading sup... » read more

Summary Of The Progress In Beta-Phase Gallium Oxide Field-Effect Transistors
By Technical Paper Link - 11 Jan, 2024 - Comments: 0

A technical paper titled “Progress in Gallium Oxide Field-Effect Transistors for High-Power and RF Applications” was published by researchers at George Mason University and National Institute of Standards and Technology (NIST). Abstract: "Power electronics are becoming increasingly more important, as electrical energy constitutes 40% of the total primary energy usage in the USA and is exp... » read more

Demonstrating A 2D–0D Hybrid Optical Multi-Level Memory Device Operated By Laser Pulses
By Technical Paper Link - 11 Jan, 2024 - Comments: 0

A technical paper titled “Probing Optical Multi-Level Memory Effects in Single Core–Shell Quantum Dots and Application Through 2D-0D Hybrid Inverters” was published by researchers at Korea Institute of Science and Technology (KIST), Korea University, Daegu Gyeongbuk Institute of Science and Technology (DGIST), National Institute for Materials Science (Japan), and University of Science and... » read more

Efficient LLM Inference With Limited Memory (Apple)
By Technical Paper Link - 04 Jan, 2024 - Comments: 0

A technical paper titled “LLM in a flash: Efficient Large Language Model Inference with Limited Memory” was published by researchers at Apple. Abstract: "Large language models (LLMs) are central to modern natural language processing, delivering exceptional performance in various tasks. However, their intensive computational and memory requirements present challenges, especially for device... » read more

Challenges And Innovations Of HW Security And Trust For Chiplet-Based 2.5D and 3D ICs
By Technical Paper Link - 04 Jan, 2024 - Comments: 0

A technical paper titled “On hardware security and trust for chiplet-based 2.5D and 3D ICs: Challenges and Innovations” was published by researchers at STMicroelectronics Crolles (ST-CROLLES), Département Systèmes et Circuits Intégrés Numériques (DSCIN), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Laboratoire Systèm... » read more

Design Space Simulator Of Distributed Multi-Chiplet Manycore Architectures For Comm-Intensive Applications
By Technical Paper Link - 04 Jan, 2024 - Comments: 0

A technical paper titled “Muchisim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems” was published by researchers at Princeton University. Abstract: "Current design-space exploration tools cannot accurately evaluate communication-intensive applications whose execution is data-dependent (e.g., graph analytics and sparse linear algebra) on scale-out manycore sys... » read more

8-In-1 Reconfigurable Logic Gate (TU Dresden)
By Technical Paper Link - 03 Jan, 2024 - Comments: 0

A technical paper titled “The RGATE: an 8-in-1 Polymorphic Logic Gate Built from Reconfigurable Field Effect Transistors” was published by researchers at TU Dresden and NaMLab. Abstract: "We present the hardware implementation of a reconfigurable universal logic gate, that we call RGATE, able to deliver up to eight different logic functionalities and based on a symmetric four-transistors... » read more

Large-Scale Integration Of 2D Materials As The Semiconducting Channel In An In-Memory Processor (EPFL)
By Technical Paper Link - 03 Jan, 2024 - Comments: 0

A technical paper titled “A large-scale integrated vector-matrix multiplication processor based on monolayer molybdenum disulfide memories” was published by researchers at École Polytechnique Fédérale de Lausanne (EPFL). Abstract: "Data-driven algorithms—such as signal processing and artificial neural networks—are required to process and extract meaningful information from the mass... » read more

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