Author's Latest Posts


Energy Usage in Layers Of Computing (SLAC)


A technical paper titled “Energy Estimates Across Layers of Computing: From Devices to Large-Scale Applications in Machine Learning for Natural Language Processing, Scientific Computing, and Cryptocurrency Mining” was published by researchers at SLAC National Laboratory and Stanford University. Abstract: "Estimates of energy usage in layers of computing from devices to algorithms have bee... » read more

A Study Of LLMs On Multiple AI Accelerators And GPUs With A Performance Evaluation


A technical paper titled “A Comprehensive Performance Study of Large Language Models on Novel AI Accelerators” was published by researchers at Argonne National Laboratory, State University of New York, and University of Illinois. Abstract: "Artificial intelligence (AI) methods have become critical in scientific applications to help accelerate scientific discovery. Large language models (L... » read more

FeFET Multi-Level Cells For In-Memory Computing In 28nm


A technical paper titled “First demonstration of in-memory computing crossbar using multi-level Cell FeFET” was published by researchers at Robert Bosch, University of Stuttgart, Indian Institute of Technology Kanpur, Fraunhofer IPMS, RPTU Kaiserslautern-Landau, and Technical University of Munich. Abstract: "Advancements in AI led to the emergence of in-memory-computing architectures as a... » read more

LLMs For Hardware Design Verification


A technical paper titled “LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation” was published by researchers at University of Cambridge, lowRISC, and Imperial College London. Abstract: "Test stimuli generation has been a crucial but labor-intensive task in hardware design verification. In this paper, we revolutionize this process by harnessing the power of large langua... » read more

GNN-Based Pre-Silicon Power Side-Channel Analysis Framework At RTL Level


A technical paper titled “SCAR: Power Side-Channel Analysis at RTL-Level” was published by researchers at University of Texas at Dallas, Technology Innovation Institute and University of Illinois Chicago. Abstract: "Power side-channel attacks exploit the dynamic power consumption of cryptographic operations to leak sensitive information of encryption hardware. Therefore, it is necessary t... » read more

Four Vertical Power Delivery Architectures For Emerging Packaging and Integration Platforms (UIC)


A technical paper titled “Vertical Power Delivery for Emerging Packaging and Integration Platforms – Power Conversion and Distribution” was published by researchers at University of Illinois Chicago. Abstract: "Efficient delivery of current from PCB to point-of-load (POL) is a primary concern in modern high-power high-density integrated systems. Traditionally, a 48 V power signal is con... » read more

Embedded Automotive Platforms: Evaluating Power And Performance Of Image Classification And Objects Detection CNNs 


A technical paper titled “Performance/power assessment of CNN packages on embedded automotive platforms” was published by researchers at University of Modena and Reggio Emilia. Abstract: "The rise of power-efficient embedded computers based on highly-parallel accelerators opens a number of opportunities and challenges for researchers and engineers, and paved the way to the era of edge com... » read more

Scalable And Compact Multi-Bit CAM Designs Using FeFETs


A technical paper titled “SEE-MCAM: Scalable Multi-bit FeFET Content Addressable Memories for Energy Efficient Associative Search” was published by researchers at Zhejiang University, China, Georgia Institute of Technology, University of California Irvine, Rochester Institute of Technology, University of Notre Dame, and Laboratory of Collaborative Sensing and Autonomous Unmanned Systems of ... » read more

An Overview Of Current Projects In The Open Quantum Hardware Ecosystem With Recommendations 


A technical paper titled “Open Hardware in Quantum Technology” was published by researchers at Unitary Fund, Qruise, Technical University of Valencia, M-Labs Limited, Lawrence Berkeley National Laboratory, Fermi National Accelerator Laboratory, Sandia National Laboratories, IQM Quantum Computers, PASQAL, Quantonation, Michigan State University, Università di Camerino, Microsoft Quantum, an... » read more

Patterning With EUV Lithography Without Photoresists


A technical paper titled “Resistless EUV lithography: photon-induced oxide patterning on silicon” was published by researchers at Paul Scherrer Institute, University College London, ETH Zürich, and EPFL. Abstract: "In this work, we show the feasibility of extreme ultraviolet (EUV) patterning on an HF-treated Si(100) surface in the absence of a photoresist. EUV lithography is the leading ... » read more

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