Author's Latest Posts


An Open-Source Solution To Accelerate Autonomous Vehicle Validation And Verification Research


A technical paper titled “PolyVerif: An Open-Source Environment for Autonomous Vehicle Validation and Verification Research Acceleration” was published by researchers at Florida Polytechnic University, Embry-Riddle Aeronautical University, Tallinn University of Technology, and Acclivis Technologies. Abstract: "Validation and Verification (V&V) of Artificial Intelligence (AI) based cyb... » read more

How A Fault-Tolerant Quantum Memory Could Be Realized Using Near-Term Quantum Processors With Small Qubit Overhead


A technical paper titled “High-threshold and low-overhead fault-tolerant quantum memory” was published by researchers at IBM T.J. Watson Research Center and MIT-IBM Watson AI Lab. Abstract: "Quantum error correction becomes a practical possibility only if the physical error rate is below a threshold value that depends on a particular quantum code, syndrome measurement circuit, and a decod... » read more

Investigating The Ru/Ta Bilayer As An Alternative EUV Absorber To Mitigate Mask 3D Effects


A technical paper titled “Ru/Ta bilayer approach to EUV mask absorbers: Experimental patterning and simulated imaging perspective” was published by researchers at KU Leuven and imec. Abstract: "The optical properties and geometry of EUV mask absorbers play an essential role in determining the imaging performance of a mask in EUV lithography. Imaging metrics, including Normalized Imag... » read more

Contacting Individual On-Surface Synthesized Graphene Nanoribbons In A Multigate Transistor Geometry 


A technical paper titled “Contacting individual graphene nanoribbons using carbon nanotube electrodes” was published by researchers at Swiss Federal Laboratories for Materials Science and Technology, Peking University, University of Warwick, National Center for Nanoscience and Technology (China), Max Planck Institute for Polymer Research, University of Bern, University of Basel, and ETH Zur... » read more

An Energy-Efficient 10T SRAM In-Memory Computing Macro Architecture For AI Edge Processor


A technical paper titled “An energy-efficient 10T SRAM in-memory computing macro for artificial intelligence edge processor” was published by researchers at Atal Bihari Vajpayee-Indian Institute of Information Technology and Management (ABV-IIITM). Abstract: "In-Memory Computing (IMC) is emerging as a new paradigm to address the von-Neumann bottleneck (VNB) in data-intensive applications.... » read more

An Open-Source Hardware Design And Specification Language To Improve Productivity And Verification 


A technical paper titled “PEak: A Single Source of Truth for Hardware Design and Verification” was published by researchers at Stanford University. Abstract: "Domain-specific languages for hardware can significantly enhance designer productivity, but sometimes at the cost of ease of verification. On the other hand, ISA specification languages are too static to be used during early stage d... » read more

Distributed Batteries Within A Heterogeneous 3D IC To Optimize Performance


A technical paper titled “On-Chip Batteries as Distributed Energy Sources in Heterogeneous 2.5D/3D Integrated Circuits” was published by researchers at University of Florida and Brookhaven National Laboratory. Abstract: "Energy efficiency in digital systems faces challenges due to the constraints imposed by small-scale transistors. Moreover, the growing demand for portable consumer electr... » read more

Formally Modeling A Security Monitor For Virtual Machine-Based Confidential Computing Systems (IBM)


A technical paper titled “Towards a Formally Verified Security Monitor for VM-based Confidential Computing” was published by researchers at IBM Research and IBM T.J. Watson Research Center. Abstract: "Confidential computing is a key technology for isolating high-assurance applications from the large amounts of untrusted code typical in modern systems. Existing confidential computing syste... » read more

Hardware-Assisted Malware Analysis


A technical paper titled "On the Feasibility of Malware Unpacking via Hardware-assisted Loop Profiling" was published by researches at Shandong University & Hubei Normal University, Tulane University and University of Texas at Arlington.  This paper was included at the recent 32nd USENIX Security Symposium. Abstract "Hardware Performance Counters (HPCs) are built-in registers of modern... » read more

Transient Execution Attacks That Leaks Arbitrary Kernel Memory (ETH Zurich)


A technical paper titled “Inception: Exposing New Attack Surfaces with Training in Transient Execution” was published by researchers at ETH Zurich. Abstract: "To protect against transient control-flow hijacks, software relies on a secure state of microarchitectural buffers that are involved in branching decisions. To achieve this secure state, hardware and software mitigations restrict or... » read more

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