Author's Latest Posts


Characteristics of Three-Gated Reconfigurable FETs


A new technical paper titled "Insights into the Temperature Dependent Switching Behaviour of Three-Gated Reconfigurable Field Effect Transistors" was published by researchers at NaMLAB and TU Dresden. "In this work, it is possible to assess the performances of Three-Gated Reconfigurable Field Effect Transistors within a considerable temperature span and finally provide significant insights o... » read more

Neuromorphic Computing: Self-Adapting HW With ReRAMs


A new technical paper titled "A self-adaptive hardware with resistive switching synapses for experience-based neurocomputing" was published by researchers at Infineon Technologies, Politecnico di Milano and IUNET, Weebit Nano, and CEA Leti. Abstract "Neurobiological systems continually interact with the surrounding environment to refine their behaviour toward the best possible reward. Achie... » read more

Using Photonic Band Gap in Triangular SiC Structures for Efficient Quantum Nanophotonic HW


A new technical paper titled "Utilizing photonic band gap in triangular silicon carbide structures for efficient quantum nanophotonic hardware" was published by researchers at UC Davis. Abstract: "Silicon carbide is among the leading quantum information material platforms due to the long spin coherence and single-photon emitting properties of its color center defects. Applications of silico... » read more

Combination of AI Techniques To Find The Best Ways to Place Transistors on Silicon Chips


A new technical paper titled "AutoDMP: Automated DREAMPlace-based Macro Placement" was published by researchers at NVIDIA. Abstract: "Macro placement is a critical very large-scale integration (VLSI) physical design problem that significantly impacts the design power-performance-area (PPA) metrics. This paper proposes AutoDMP, a methodology that leverages DREAMPlace, a GPU-accelerated place... » read more

Covert Channel Between the CPU and An FPGA By Modulating The Usage of the Power Distribution Network


A new technical paper titled "CPU to FPGA Power Covert Channel in FPGA-SoCs" was published by researchers at TU Munich and Fraunhofer Research Institution AISEC. Abstract: "FPGA-SoCs are a popular platform for accelerating a wide range of applications due to their performance and flexibility. From a security point of view, these systems have been shown to be vulnerable to various attacks... » read more

Large Area Process For Atomically Thin 2D Semiconductor, Using Scalable ALD


A new technical paper titled "Large-area synthesis of high electrical performance MoS2  by a commercially scalable atomic layer deposition process" by researchers at the University of Southampton, LMU Munich, and VTT Technical Research Centre of Finland. Abstract: "This work demonstrates a large area process for atomically thin 2D semiconductors to unlock the technological upscale required... » read more

CXL Memory: Detailed Characterization Analysis Using Micro-Benchmarks And Real Applications (UIUC, Intel Labs)


A new technical paper titled "Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices" was published by researchers at University of Illinois Urbana-Champaign (UIUC) and Intel Labs. Abstract: "The high demand for memory capacity in modern datacenters has led to multiple lines of innovation in memory expansion and disaggregation. One such effort is Compute eXpress Link (CXL)-based... » read more

Hardware Based Monitoring For Zero Trust Environments


A technical paper titled "Towards Hardware-Based Application Fingerprinting with Microarchitectural Signals for Zero Trust Environments" was published by the Air Force Institute of Technology. Abstract "The interactions between software and hardware are increasingly important to computer system security. This research collects sequences of microprocessor control signals to develop machine ... » read more

Interconnects: Exploring Semi-Metals (Penn State, IBM, Rice University)


A technical paper titled "Exploring Topological Semi-Metals for Interconnects" was published by researchers at Penn State, IBM, and Rice University, with funding by Semiconductor Research Corporation (SRC). Abstract "The size of transistors has drastically reduced over the years. Interconnects have likewise also been scaled down. Today, conventional copper (Cu)-based interconnects face a ... » read more

Logic Locking at the RTL, Leveraging The Behavioral State Transition Coding For Obfuscation (University of Florida)


A new technical paper titled "ReTrustFSM: Toward RTL Hardware Obfuscation-A Hybrid FSM Approach" was published by researchers at University of Florida, Gainesville, FL. Abstract: "Hardware obfuscating is a proactive design-for-trust technique against IC supply chain threats, i.e., IP piracy and overproduction. Many studies have evaluated numerous techniques for obfuscation purposes. Neverth... » read more

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