Author's Latest Posts


Nonvolatile ECRAM With A Short-Circuit Retention Time Several Orders of Magnitude Higher Than Previously Shown


A new technical paper titled "Nonvolatile Electrochemical Random-Access Memory Under Short Circuit" was published by researchers at University of Michigan and Sandia National Laboratories. Abstract "Electrochemical random-access memory (ECRAM) is a recently developed and highly promising analog resistive memory element for in-memory computing. One longstanding challenge of ECRAM is attainin... » read more

Locking-Based Design-For-Security Methodology To Prevent Piracy of RF transceiver ICs


A new technical paper titled "Anti-Piracy Design of RF Transceivers" was published by researchers at Sorbonne Universite (France). Abstract: "We present a locking-based design-for-security methodology to prevent piracy of RF transceiver integrated circuits. The solution is called SyncLock as it locks the synchronization of the transmitter with the receiver. If a key other than the secret ... » read more

On-chip 2D/3D Photonics Integration Solution Using Deposited Polycrystalline Silicon for Optical Interconnects Applications


A new technical paper titled "Polycrystalline silicon PhC cavities for CMOS on-chip integration" was published by researchers at Tyndall National Institute, Munster Technological University, and Université Grenoble Alpes, CEA, LETI. "In this work, we present an on-chip 2D and 3D photonics integration solution compatible with Front End of Line integration (FEOL) using deposited polycrystalli... » read more

Simulating the Groundstate and Dynamics of Quantum Critical Systems


A new technical paper titled "Simulating groundstate and dynamical quantum phase transitions on a superconducting quantum computer" was published by researchers at London Centre for Nanotechnology, University College London, University of Massachusetts, and Google Quantum AI. Abstract (partial) "The phenomena of quantum criticality underlie many novel collective phenomena found in condensed... » read more

Wafer Scale Tool To Transfer Graphene


A new technical paper titled "Assessment of wafer-level transfer techniques of graphene with respect to semiconductor industry requirements" was published by researchers at RWTH Aachen University, AMO GmbH, Infineon Technologies, Protemics GmbH, and Advantest Europe. Abstract (partial): "Graphene is a promising candidate for future electronic applications. Manufacturing graphene-based elect... » read more

Hardware Platform Based on 2D Memtransistors


A new technical paper titled "Hardware implementation of Bayesian network based on two-dimensional memtransistors" from researchers at Penn State University. "In this work, we demonstrate hardware implementation of a BN [Bayesian networks] using a monolithic memtransistor technology based on two-dimensional (2D) semiconductors such as monolayer MoS2. First, we experimentally demonstrate a lo... » read more

Thermal Scanning Probe Lithography


A new technical paper titled "Edge-Contact MoS2 Transistors Fabricated Using Thermal Scanning Probe Lithography" was published by researchers at École Polytechnique Fédérale de Lausanne (EPFL). "Thermal scanning probe lithography (t-SPL) is a gentle alternative to the typically used electron beam lithography to fabricate these devices avoiding the use of electrons, which are well known to... » read more

RISC-V Virtual Prototype


A new technical paper titled "Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype" was published by researchers at DFKI GmbH and University of Bremen. Abstract "RISC-V is a modern Instruction Set Architecture (ISA) that, by its open nature in combination with a clean and modular design, has enormous potential to become a game changer in the Internet o... » read more

Automating The Detection of Hardware Common Weakness Enumerations In Early Design


A new technical paper titled "Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design" was published by researchers at NYU, Intel, Duke and University of Calgary. "To help prevent hardware security vulnerabilities from propagating to later design stages where fixes are costly, it is crucial to identify security concerns as early as possible, such as in RTL designs. ... » read more

A Full-Stack Domain-Specific Overlay Generation Framework Verified On FPGA


A new technical paper titled "OverGen: Improving FPGA Usability through Domain-specific Overlay Generation" by researchers at UCLA and Chinese Academy of Sciences. "Our essential idea is to develop a hardware generation framework targeting a highly-customizable overlay, so that the abstraction gap can be lowered by tuning the design instance to applications of interest. We leverage and ext... » read more

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