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Training a ML model On An Intelligent Edge Device Using Less Than 256KB Memory
By Technical Paper Link - 11 Oct, 2022 - Comments: 0

A new technical paper titled "On-Device Training Under 256KB Memory" was published by researchers at MIT and MIT-IBM Watson AI Lab. “Our study enables IoT devices to not only perform inference but also continuously update the AI models to newly collected data, paving the way for lifelong on-device learning. The low resource utilization makes deep learning more accessible and can have a bro... » read more

Transistor-Free Compute-In-Memory Architecture
By Technical Paper Link - 11 Oct, 2022 - Comments: 0

A new technical paper titled "Reconfigurable Compute-In-Memory on Field-Programmable Ferroelectric Diodes" was recently published by researchers at University of Pennsylvania, Sandia National Labs, and Brookhaven National Lab. The compute-in-memory design is different as it is completely transistor-free. “Even when used in a compute-in-memory architecture, transistors compromise the access... » read more

Highly Dense And Vertically Aligned Sub-5 nm Silicon Nanowires
By Technical Paper Link - 11 Oct, 2022 - Comments: 0

A new technical paper titled "Catalyst-free synthesis of sub-5 nm silicon nanowire arrays with massive lattice contraction and wide bandgap" was published by researchers at Northeastern University, Korea Institute of Science and Technology, Gyeongsang National University and others. "Here, we prepare highly dense and vertically aligned sub-5 nm silicon nanowires with length/diameter aspect r... » read more

Accelerating Off-Chip Load Requests By Removing The On-Chip Cache Access Latency From Their Critical Path
By Technical Paper Link - 11 Oct, 2022 - Comments: 0

A new technical paper titled "Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction" was published by researchers at ETH Zurich, Intel Processor Architecture Research Lab, and LIRMM, Univ. Montpellier, CNRS.  The work received a best paper award at MICRO 2022. Abstract "Long-latency load requests continue to limit the performance of high-performance ... » read more

More Efficient Matrix-Multiplication Algorithms with Reinforcement Learning (DeepMind)
By Technical Paper Link - 11 Oct, 2022 - Comments: 0

A new research paper titled "Discovering faster matrix multiplication algorithms with reinforcement learning" was published by researchers at DeepMind. "Here we report a deep reinforcement learning approach based on AlphaZero for discovering efficient and provably correct algorithms for the multiplication of arbitrary matrices," states the paper. Find the technical paper link here. Publis... » read more

Functional Safety Verification Of Serial Peripheral Interface
By Technical Paper Link - 03 Oct, 2022 - Comments: 0

A new technical paper titled "FMEDA based Fault Injection to Validate Safety Architecture of SPI" was published by researchers at R.V. College of Engineering in India and Analog Devices. Abstract "The integration of advanced technologies into Electrical Vehicles (EV) has been increasing in recent times, so it has become crucial to evaluate the risk of the technologies that are deployed into... » read more

Speeding-Up Thermal Simulations Of Chips With ML
By Technical Paper Link - 02 Oct, 2022 - Comments: 0

A new technical paper titled "A Thermal Machine Learning Solver For Chip Simulation" was published by researchers at Ansys. Abstract "Thermal analysis provides deeper insights into electronic chips' behavior under different temperature scenarios and enables faster design exploration. However, obtaining detailed and accurate thermal profile on chip is very time-consuming using FEM or CFD. Th... » read more

Adaptive Memristive Hardware
By Technical Paper Link - 02 Oct, 2022 - Comments: 0

A new technical paper titled "Self-organization of an inhomogeneous memristive hardware for sequence learning" was just published by researchers at University of Zurich, ETH Zurich, Université Grenoble Alpes, CEA, Leti and Toshiba. "We design and experimentally demonstrate an adaptive hardware architecture Memristive Self-organizing Spiking Recurrent Neural Network (MEMSORN). MEMSORN incorp... » read more

Six Qubit Processor (TU Delft, QuTech, TNO)
By Technical Paper Link - 29 Sep, 2022 - Comments: 0

A new technical paper titled "Universal control of a six-qubit quantum processor in silicon" was just published by researchers at Delft University of Technology, QuTech and Netherlands Organization for Applied Scientific Research (TNO). "We increase the number of qubits and simultaneously achieve respectable fidelities for universal operation, state preparation and measurement. We design, fa... » read more

Framework Based on an RISC-V Microprocessor Supporting LiM Operations
By Technical Paper Link - 29 Sep, 2022 - Comments: 0

A new technical paper titled "RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures" was published by researchers at Politecnico di Torino (Italy), Univerity of Tor Vergata (Italy), and University of Twente (The Netherlands). Abstract: "Most modern CPU architectures are based on the von Neumann principle, where memory and processing units are separate entities. Although processin... » read more

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