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Model-Based Double-Dipole Lithography For Sub-30nm Node Device
By Various Writers - 26 Jun, 2012 - Comments: 0

As the optical lithography advances into the sub-30nm technology node, the various candidates of lithography have been discussed. Double dipole lithography (DDL) has been a primary lithography candidate due to the advantages of a simpler process and a lower mask cost compared to the double patterning lithography (DPL). However, new DDL requirements have been also emerged to improve the process ... » read more

What’s ST’s FD-SOI Technology All About?
By Various Writers - 22 Jun, 2012 - Comments: 0

As I blogged here on SemiMD last week, STMicroelectronics has announced that to supplement in-house production at their fab in Crolles, the company has tapped GlobalFoundries for high-volume production of 28nm then 20nm FD-SOI mobile devices.  ST will also open access to its FD-SOI technology to GlobalFoundries’ other customers.  High-volume manufacturing will kick off with ST-Ericsson’s ... » read more

GloFo to Fab 28/20nm FD-SOI for ST; ST Tech Open to GF Customers
By Various Writers - 15 Jun, 2012 - Comments: 0

Two big pieces of news have recently been announced by STMicroelectronics: to supplement in-house production at Crolles, the company has tapped GlobalFoundries for high-volume production of 28nm then 20nm FD-SOI mobile devices; ST will open access to its FD-SOI technology to GlobalFoundries’ other customers. The high-volume manufacturing will kick off with ST-Ericsson’s ARM-based 2... » read more

Lint Your Hardware Description: The Need To Be Fast, Accurate, Scalable And Flexible
By Various Writers - 14 Jun, 2012 - Comments: 0

A reliable linting tool must be SAFE (Scalable, Accurate, Fast and Extendible) so it can help catch issues early in the design cycle - issues that may be missed by traditional dynamic verification techniques. The main objective of a SAFE linting solution is to reduce costly design iterations, prevent late stage design ECOs and promote seamless reuse of IPs. Such a linting solution will need to ... » read more

Power And Signal Line Electromigration Design And Reliability Validation Challenges
By Various Writers - 14 Jun, 2012 - Comments: 0

This white paper describes EM integrity analysis for power and signal lines. It outlines the various process and design trends that are increasing the likelihood of EM-induced failures in a design and looks at conventional verification techniques for EM integrity and contrasts those with what is required for advanced process nodes. To download this paper, click here. » read more

Chenming Hu: SOI Can Empower New Transistors to 10nm and beyond
By Various Writers - 30 May, 2012 - Comments: 0

The following is a special guest post by Dr. Chenming Hu, TSMC Distinguished Professor at UC Berkeley. He and his team published seminal papers on FinFETs (1999) and UTB-SOI (2000). This post first appeared as part of the Advanced Substrate News special edition on FD-SOI industrialization.  ~~ The good, old MOSFET is nearing its limits. Scaling issues and dopant-induced variations ... » read more

28nm Super Low Power CMOS
By Various Writers - 29 May, 2012 - Comments: 0

28nm Super Low Power (28nm-SLP) is the low-power CMOS offering delivered on bulk silicon substrate for mobile consumer and digital consumer applications. GlobalFoundries' 28nm-SLP process technology is designed for the next generation of smart mobile devices, enabling designs with faster GHz processing speeds, higher circuit density, lower standby power and longer battery life. The 28nm process... » read more

Planar Fully Depleted Silicon Technology To Design Competitive SoCs At 28nm And Beyond
By Various Writers - 29 May, 2012 - Comments: 0

This document considers the challenges to obtain competitive silicon technology for the upcoming generation of System-On-Chip ICs. It suggests planar fully depleted technology deserves serious interest. After outlining some implementation choices, a number of circuit-level benchmark results as well as some important design aspects are presented. It is found that this technology combines high pe... » read more

Finding And Eliminating Hot Spots
By Various Writers - 29 May, 2012 - Comments: 0

With the continuous development of today’s technology, IC design becomes a more complex process. The designer now not only takes care of the normal design and layout parameters as usual, but also needs to consider the process variation impact on the design to preserve the same chip functionality with no failure during fabrication. In the current process, schematic designers go through extensi... » read more

Soitec’s Wafer Roadmap for Fully Depleted Planar and 3D/FinFET
By Various Writers - 24 May, 2012 - Comments: 0

The following is a special guest post by Steve Longoria, Senior VP of Worldwide Business Development at Soitec.  It first appeared as part of the Advanced Substrate News special edition on FD-SOI industrialization. ~~ Today’s semiconductor industry is moving through several challenging transitions that are creating a significant opportunity for Soitec to bring incremental value to th... » read more

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