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eDRAM: No Brainer…But No Takers?
By Various Writers - 20 Oct, 2011 - Comments: 0

By Steve Hamilton Designers in the consumer electronics market—mobile in particular—are constantly looking for new ways to reduce cost and power while increasing performance. This is far from novel. With consumers’ unrelenting demand for more features at lower prices, you would think semiconductor companies would jump when confronted with a technology that gives them a real competitive e... » read more

Understanding Formal Verification Concepts, Part 3
By Various Writers - 20 Oct, 2011 - Comments: 0

This final white paper in a three-part series about formal verification concepts examines the assertion-based verification flow and some of the formal verification algorithms. To download the first two papers in this series, click here for part one and here for part two. This kind of approach has become necessary as SoC designs become more challenging and the traditional method of simulat... » read more

Power and Noise Integrity for Analog/Mixed-Signal Designs
By Various Writers - 06 Oct, 2011 - Comments: 0

This paper describes the need for power noise integrity solution for analog / mixed-signal designs and the benefits of the Totem platform, its usage model in a design flow, and results from simulation and correlation measurements. To download this paper, click here. » read more

Ultra-thin wafers for 450mm FD-SOI on schedule
By Various Writers - 03 Oct, 2011 - Comments: 0

While much of the focus on the impending move to 450mm has focused on the equipment challenges, the wafers themselves are of course the primordial consideration. Predictions are starting to mount up linking the move to 450mm with a move to fully-depleted silicon-on-insulator (FD-SOI). So the question needs to be asked: will the wafers be ready? Engineered substrates like SOI wafers need to ... » read more

FD-SOI Foundations Ready, Say Semi Execs
By Various Writers - 09 Sep, 2011 - Comments: 0

By Adele Hars SOI (especially fully depleted “FD-SOI”) was a hot topic in the video and audio interviews that Debra Vogler of SST released recently. Here are brief summaries of the most important SOI-related interviews – with top brass from Leti, Soitec, KT, EVG and Qcept –  that she made at Semicon West ’11. (If you need a quick backgrounder on FD-SOI basics, see this exp... » read more

Picking The Right Models
By Various Writers - 08 Sep, 2011 - Comments: 0

By Ji Zheng As the focus on “efficient computing” increases and ICs are fabricated using process technologies that are more sensitive to voltage fluctuations, accurate modeling and prediction of chip-level, package-level and system-level behavior becomes a necessary design step. The use of chip macro models enables 3D-IC and IC-package-PCB co-analysis for power integrity, signal integrity,... » read more

Summertime…And The Living (Isn’t) Easy
By Various Writers - 25 Aug, 2011 - Comments: 0

By Jack Browne Normally summer is a time where most people slow down, relax, take vacations and the pace slows down accordingly with the seasonal ebb and flow of our industry. But not this summer. Exhibit A, B, C, D and so on: This past month has demonstrated the profound element of change. Mostly in our wallets. The stock market volatility and global economic disruptions have echoed (an... » read more

Does SOI matter to the designers using the chips?
By Various Writers - 19 Aug, 2011 - Comments: 0

By Adele Hars Much of the SOI vs. bulk discussion zeros right in on the manufacturing bottom line:  which is cheaper?   And absolutely, customers want the most cost-effective solution.  But the best of all possible worlds is if you can save them money and give them all the bells and whistles they're looking for, too, right? [caption id="attachment_150" align="alignleft" width="150" capti... » read more

Study Shows FD-SOI Most Cost-Effective Approach at 22nm
By Various Writers - 02 Aug, 2011 - Comments: 0

By Adele Hars What are you doing at 22nm? The debate is raging in the press and forums alike. Now research firm IC Knowledge has issued a report showing that from a straight cost perspective, planar FD-SOI is a better choice than bulk. We’ve known for a while that sticking with bulk at the 22nm node would get pretty complicated. This study shows just how complicated bulk will be: abou... » read more

Understanding Formal Verification Concepts, Part II
By Various Writers - 28 Jul, 2011 - Comments: 0

In this second white paper in a three-part series about formal verification concepts, we examine the assertion-based verification flow and some of the formal verification algorithms. This kind of approach has become necessary as SoC designs become more challenging and as the traditional method of simulation proves too slow, too costly, and insufficient in terms of coverage. To downoload thi... » read more

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