Picking The Right Models

Chip macro modeling is essential for accurately predicting chip-, package- and system-level behavior.


By Ji Zheng
As the focus on “efficient computing” increases and ICs are fabricated using process technologies that are more sensitive to voltage fluctuations, accurate modeling and prediction of chip-level, package-level and system-level behavior becomes a necessary design step. The use of chip macro models enables 3D-IC and IC-package-PCB co-analysis for power integrity, signal integrity, EMI and thermal related reliability.

A comprehensive chip-package-PCB system validation flow requires an accurate model for each component in order to enable cross-domain data sharing. An accurate model of the IC is very complex, given the “active” behavior, its dependence on the stimulus and mode of operation, plus its size and density. Since it is difficult to encapsulate in one single model the various pieces of information needed for the entire system-level analyses, different models must be created to enable each of these analyses.

Chip power model
One key innovation is chip power model (CPM) technology—a multi-port, simultaneously multi-domain, layout-based electrical representation of the chip in an open SPICE format. It captures switching and leakage current, and parasitic elements present in the chip. It can mimic the behavior of a fully detailed chip layout, consisting of power/ground routing (with RLC parasitics), and the devices with their associated current, capacitance and resistance from DC to multi-GHz range. The CPM can handle an entire chip layout with device information. It captures an extracted on-die power delivery network (PDN) parasitics and coupling, all device and other capacitances, and reduce large netlists (with more than 100 million nodes) into a behavioral model that can be interpreted and simulated by SPICE engines.

Chip thermal model
A chip thermal model (CTM) captures information that is needed for package-level thermal analysis and is a temperature-dependent IC power consumption model. Similar to the CPM, a CTM is created from a simulation. To generate a CTM, the power for the chip is calculated at the cell-level at multiple temperatures points. It then partitions the design into multiple regions, and maps the power of the instances (or transistors) in each region to form a “region-specific” power-temperature table capturing the switching, self-heat and leakage power in that region as a function of temperature. In addition to the power-temperature data, the CTM also captures the layer-by-layer density of the interconnect geometries in the design for each region.

Traditionally, thermal analysis of a system has been done using highly abstracted models of the components. However, analysis with abstract models impacts not only the quality of the system-level analysis and associated engineering decisions, but it also prevents the flow of data back to the IC designer, to model and quantify the impact of the thermal profiles on the IC’s performance and long term reliability.

Chip signal model
The need to exchange digital information between communicating chips at faster rates has significantly impacted noise and timing margins. So when simulating a system, it is important to include accurate models of each component of the complete system that supplies, generates, or transmits the signal. A chip signal model (CSM) provides an accurate model of the on-chip power delivery network (PDN), as well as the cell I/O macro-model for the I/O buffers. The I/O macro model used in CSM is more efficient than the original transistor netlist model, with much better accuracy than IBIS, and it leaves the underlying IP opaque and protected.

Accurate and high-capacity package/PCB simulation
As the complexity of package design increases and package/PCB design teams look at optimizing the number of layers and discrete elements they use, accurate modeling of these structures to help determine the right design trade-offs is becoming critical. It is well known that to accurately capture complex structures such as vias, cut-outs, non-ideal ground planes, etc., employing 3D full-wave modeling technologies that can capture effects including field fringing and boundary reflections is key. However, existing 3D full-wave modeling and extraction technologies are capacity limited, forcing designers to cut out portions of the package/PCB.

Optimal solutions allow designers to simulate and model entire package/PCB geometries. This approach should solve the complete set of Maxwell’s equations to generate broadband model representations of the package/PCB power/ground and signal nets.

System convergence covers a wide range of co-design related issues. A CPM can be used to accurately model the switching power and parasitics of the die. The CTM, which is a thermal model of the chip, can be used to accurately solve the power-temperature loop and measure temperature effects on leakage power and thermal stress. The CSM provides an accurate model of the on-chip I/O ring, including the I/O devices and decaps. By using advanced modeling and proven simulator technologies, solutions for chip-package-system convergence are changing outdated compartmentalized chip, package, and board design methodologies by enabling intelligent, integrated, system-aware designs.

–Ji Zheng is R&D director at Apache Design Solutions.

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