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MEMS on SOI – Growing Fast and Faster
By Various Writers - 11 Apr, 2011 - Comments: 0

By Adele Hars In the latest ASN posting by Dr. Eric Mounier of Yole Developpement, “SOI for MEMS: A Promising Material”, he notes that SOI MEMS is growing at a CAGR (2011-2015) of 15.6%, compared to 8.1% for bulk silicon-based solutions. MEMS designers are doing amazing things on SOI – which would explain that impressive growth rate. [caption id="attachment_12" align="aligncenter... » read more

The SOI Papers at ISSCC 2011
By Various Writers - 15 Mar, 2011 - Comments: 0

By Adele Hars The International Solid-State Circuits Conference — better known as ISSCC — is of course where the big guns show us their big advances at the chip level. At the most recent conference, held a few weeks ago in San Francisco, advances that leveraged SOI were once again at the forefront. As always, performance gains generate plenty of buzz. But the SOI papers were also nota... » read more

Design Impacts of Fully Depleted SOI
By Various Writers - 10 Feb, 2011 - Comments: 0

Xavier Cauchy, digital applications manager at Soitec, considers the design implications of fully depleted SOI technology, including models, low-power techniques for SoCs, and other issues at the 22nm node. “Compelling simulation and silicon data for nanometer scale transistors is becoming available. However, as potential users realize the many interests of this technology, the next question ... » read more

Frequently Asked Questions About FD-SOI
By Various Writers - 10 Feb, 2011 - Comments: 0

In a question and answer format, Xavier Cauchy, digital applications manager at Soitec ([email protected]) and François Andrieu, senior research engineer at LETI, raise some of the technical issues surrounding fully depleted SOI technology. The authors compare FD-SOI to FinFETs, describe how non-digital transistors can be handled, and provide a list of references for further reading. » read more

Manufacturing Closure with Calibre InRoute and Olympus-SoC
By Various Writers - 10 Feb, 2011 - Comments: 0

Achieving manufacturing signoff is getting more difficult at each node due to significant manufacturing limitations and variability. This paper from Mentor Graphics describes the physical signoff challenges seen in advanced node designs. It then demonstrates how the Calibre InRoute platform provides faster and more reliable DRC/DFM signoff by using the Calibre verification and DFM platform to d... » read more

Metric Pitch BGA And Micro BGA Routing Solutions
By Various Writers - 08 Feb, 2011 - Comments: 0

The following paper provides Via Fanout and Trace Routing solutions for various metric pitch Ball Grid Array Packages. Note: the “metric” dimensions are the ruling numbers. To solve the metric pitch BGA dilemma, one should have a basic understanding of the metric feature sizes for: BGA Ball Sizes and BGA Land Pattern Pad Construction BGA Via Anatomy Trace/Space Trace and Via Routi... » read more

Why Settle For Good Enough
By Various Writers - 21 Oct, 2010 - Comments: 0

By Kalar Rajendiran The title of this article is missing a punctuation mark at the end and that is by design. Some readers may read it as a question and some others as a statement, depending on their frame of mind and the particular task they are focused on at that time. This article, although not intended to be a psychoanalysis of how people see and interpret what they see, does highlight how... » read more

RTL Fault Coverage Estimation
By Various Writers - 26 Aug, 2010 - Comments: 0

This paper describes a method for estimating fault coverage from register transfer level (RTL) descriptions of complex circuits. The method does not require automatic test pattern generation (ATPG) or the use of fault simulation and therefore offers the advantage of very rapid turnaround with no additional user effort. An important benefit is the means for a user to quickly determine the change... » read more

PathFinder: A Dynamic And Static Analysis Solution For IP And Full-Chip IC ESD Integrity
By Various Writers - 13 Aug, 2010 - Comments: 0

ESD or electro-static discharge induced field failures for integrated circuits (IC) has always been an challenge. Literature survey indicates that as high as 35% of total chip field failures are ESD related. Several trends in the IC industry are exacerbating the impact of ESD induced failures: (a) move towards advanced processing technologies with shrinking geometries, (b) push for higher le... » read more

Power And Signal Line Electromigration
By Various Writers - 12 Aug, 2010 - Comments: 0

Power and Signal Line Electromigration Design and Reliability Validation Challenges for the 28nm-era Reliability verification is an important aspect in the design and development of an integrated circuit to guarantee its continued functioning over years of production use. One critical area of reliability verification is electromigration (EM) check analysis to ensure that the wires and vias u... » read more

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