Power And Signal Line Electromigration

A look at the design and reliability validation challenges for the 28nm era.

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Power and Signal Line Electromigration Design and Reliability Validation Challenges for the 28nm-era

Reliability verification is an important aspect in the design and development of an integrated circuit to guarantee its continued functioning over years of production use. One critical area of reliability verification is electromigration (EM) check analysis to ensure that the wires and vias used to connect the various devices in the chip do not fail from years of continuous use. EM can result in either opens (broken wires) or shorts (from movement of metal from one wire touching another one) in metal/via interconnects. These metal wires and vias are used to connect devices to the power and ground supplies or to connect the output of one device to the input of another.

Semiconductor fabrication companies provide guidelines for maximum allowed current through a particular type of wire (or via/contact) at a particular temperature, or also referred to as “EM limits”, which are defined in Design Rule Manual (DRM) or coded directly inside process technology files (like iRCX). Often times, Black’s equation is used to predict the mean time to failure (MTTF) of interconnects in ICs by testing the devices under stress conditions such as extreme PVT (process, voltage, temperature) and operating (current density) conditions. The results from such stress tests are then extrapolated to the device’s expected life span under real conditions. By simulating a design and verifying that the current flow for both power and signal lines do not exceed these foundry specified limits, one ensures that the interconnects and hence the design itself will meet required MTTF limits.

This whitepaper provides an in-depth look at EM integrity analysis for power and signal lines. It first outlines the various process and design trends that are increasing the likelihood of EM induced failures in a design. It then looks at conventional verification techniques for EM integrity and contrasts those with what is required for advanced process nodes. The paper will also provide details on power and signal line EM analyses using Apache’s RedHawk and Totem platforms for power, noise and reliability analysis.

To download this white paper, click here.