Author's Latest Posts

Five Key Challenges In Designing With High-Speed Analog IP
By Various Writers - 12 Mar, 2014 - Comments: 0

There’s good reason why analog IC design is often considered to be more of an art than a science. Compared to their digital counterparts, analog components are much more sensitive to noise, distortion, and other errors. This white paper is filled with tips on meeting these challenges and speeding up your design cycle. To download this paper, click here. » read more

Improving Embedded Systems Reliability With A Process Model-Based RTOS
By Various Writers - 12 Mar, 2014 - Comments: 0

The introduction of Nucleus Process Model to the Nucleus Real Time Operating System (RTOS) maintains the key characteristics of an RTOS and adds many of the benefits of a large scale OS, such as dynamic task, library loading and unloading, memory access protection, and operational privilege control. This paper discusses the various dimensions of operating under the process model, including its ... » read more

Design Guidelines For Embedded Real Time Face Detection Application
By Various Writers - 12 Mar, 2014 - Comments: 0

This paper presents steps for real-time deployment of face detection application on a programmable vector processor. The steps taken are general purpose in the sense that they can be used to implement similar computer vision algorithms on any mobile device. To download this white paper, click here. » read more

Using Formal Verification Across A Spectrum Of Design Applications
By Various Writers - 12 Mar, 2014 - Comments: 0

Chip designers worldwide have told us that Jasper is fundamentally different in how we approach their technical and business problems by delivering a high ROI (return on investment) through the application of advanced formal verification techniques. Our tools address a spectrum of key verification challenges - from getting the architecture unambiguously right, to putting more power in the hands... » read more

USB 3.1: Evolution And Revolution
By Various Writers - 12 Mar, 2014 - Comments: 0

USB-IF Worldwide Developers Days introduced developers to the new USB 3.1 specification. On the surface, USB 3.1 seems like it could be only an update to 10G speeds, but this white paper will dig deeper into 10G USB 3.1 to clarify the evolutionary and revolutionary changes in the USB 3.1 specification. USB 3.1 introduces a new 10 Gbps signaling rate in addition to the 5 Gbps signaling rate defi... » read more

Virtual Prototypes For Early Software Development
By Various Writers - 26 Feb, 2014 - Comments: 0

In previous white papers, we've looked at the demands of the rapidly changing market and how the use of virtual prototypes has evolved to help meet them. In this white paper, we look specifically at the challenges of developing some of the hardware-dependent software layers - namely boot ROM code, OS bring-up, driver development - used in fast-evolving mobile devices and how to use virtual prot... » read more

Plug-And-Play Test Strategy For 3D ICs
By Various Writers - 26 Feb, 2014 - Comments: 0

As the industry transitions to 3D ICs, new test strategies are being developed to meet to two 3D IC test goals: improving the pre-packaged test quality and establishing new tests between the stacked die. Solutions for 3D IC test are developing rapidly and are based on mature technologies. In this paper, we describe a test strategy for 3D ICs based on a plug-and-play architecture that allows die... » read more

Maximizing Verification Effectiveness Using Metric-Driven Verification
By Various Writers - 26 Feb, 2014 - Comments: 0

This paper introduces the Cadence Incisive Verification Kit as a golden example of how to maximize verification effectiveness by applying metric-driven verification (MDV) in conjunction with the Universal Verification Methodology (UVM). MDV provides an overarching approach to the verification problem by transforming an open-ended, open-loop verification process into a manageable, repeatable, de... » read more

Impact Of Illumination On Model-Based SRAF Placement For Contact Patterning
By Various Writers - 19 Feb, 2014 - Comments: 1

Sub-Resolution Assist Features (SRAFs) have been used extensively to improve the process latitude for isolated and semi-isolated features in conjunction with off-axis illumination. These SRAFs have typically been inserted based upon rules which assign a global SRAF size and proximity to target shapes. Additional rules govern the relationship of assist features to one another, and for random log... » read more

How A Team-Based Approach To PCB Power Integrity Analysis Yields Better Results
By Various Writers - 12 Feb, 2014 - Comments: 0

Assuring power integrity of a PCB requires the contributions of multiple design team members. Traditionally, such an effort has involved a time-consuming process for a back-end-focused expert at the front end of a design. This paper examines a collaborative team-based approach that makes more efficient use of resources and provides more impact at critical points in the design process. To vie... » read more

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