Blog Review: Dec. 4

Siemens’ Reetika explains how creating and verifying a complete reset tree structure allows designers to trace the flow of reset signals across the design and ensure that every sequential element is tagged correctly within its respective reset domain.

Cadence’s Durlov Khan suggests DDR5 DIMM Memory Models and Discrete Component Models as part of a flexible approach to validating specific component designs with a fully populated pre-silicon environment.

Synopsys’ Gary Ruggles and Gordon Getty show off a recent CXL 3.1 multi-vendor interoperability demonstration, including how connections can be made without the assistance of an interposer.

Arm’s Alan Hayward introduces Arm Scalable Vector Extension (SVE), a SIMD architecture that allows developers to write more efficient and simpler vectorization code, and explores the main differences in concepts between Neon and SVE.

Ansys’ Susan Coleman and Emily Gerken check out how a startup uses simulation tools to develop and characterize a unique type of qubit for fault-tolerant quantum computing.

Keysight’s Elizabeth Fei warns that while the complementary capabilities of AI and IoT offer healthcare systems the ability to collect and analyze large amounts of biometric data, IoT devices connected to hospital networks often lack active management and protection, making them easy entry points for attackers.

SEMI’s Maria Daniela Perez chats with Srikanth Samavedam and Jo De Boeck of imec about the NanoIC pilot line initiative that aims to bridge the gap between R&D and industrial innovation with a beyond-2nm SoC pilot line for developing advanced logic, memory, and interconnect technologies.

And don’t miss the blogs featured in the latest Manufacturing, Packaging & Materials and Systems & Design newsletters:

Technology editor Brian Bailey suggests any optimization problem must have a clear, unambiguous specification and a way to define the goodness of the solution.

Amkor’s Vineet Pancholi explains how UCIe helps test through a fixed shoreline, multiple redundant lanes, and mission mode lane performance monitoring.

Lam Research’s James Kim shows how to address etch loading effects with layout design modification.

eBeam Initiative’s Jan Willis recaps key findings on EUV pellicles during a discussion at the 2024 SPIE Photomask and EUV conference.

ESD Alliance’s Bob Smith talks about EDA’s continued consolidation, expansion into engineering software, and other business indicators, with Jay Vleeschhouwer of Griffin Securities.

Arteris’ Andy Nightingale explains how mesh network topology ensures efficient communication between tiles, avoiding bottlenecks and allowing for parallel processing across the chip.

Alphawave Semi’s Archana Cheruliyil outlines the advantages and challenges of HBM and the quest to shrink the memory-performance gap.

Siemens’ Wael ElManhawy explores a shift-left methodology to perform LVS comparison earlier in the design flow, catching errors sooner and reducing the number of iterations required during sign-off.

Synopsys’ Samad Parekh looks at the increasing level of integration and miniaturization in PMICs driven by trends in IoT, wearables, and consumer electronics.

Keysight’s Chaimaa Aarab highlights challenges around non-terrestrial networks, Wi-Fi 7, 6G, and the growing role of AI and ML in network optimization.

Cadence’s Steve Brown delves into chiplet-based architectures and how they address issues of design complexity and yield, while significantly reducing time to market and development costs.