Blog Review: Feb. 5

Cadence’s Rajneesh Chauhan explores the extended metadata feature in CXL 3.1, which helps systems manage memory and devices more effectively by sending extra information along with memory transactions to provide more context about what’s happening during these transactions.

Siemens’ Bianca Ward recommends semiconductor companies combat rising production costs by leaning into digitalization and leveraging comprehensive digital twins for both the semiconductor design and fabrication.

Synopsys’ Faisal Goriawalla and Yervant Zorian point to the importance of UCIe interconnect monitoring, test, and repair to help ensure the quality and reliability of multi-die designs.

Keysight’s Richard Duvall highlights the need for rigorous simulation and validation to overcome challenges such as signal degradation, electromagnetic interference, crosstalk, parasitic effects, and antenna effects when designing radio frequency ICs, monolithic microwave ICs, and mixed-signal ICs.

Arm’s Jacob Bramley digs into cache maintenance in self-modifying code and the challenges of working with multiple threads.

Rambus’ Julien Eydoux showcases L0p mode and FLIT mode operation in a PCIe 6.x controller, allowing systems to adjust the number of active lanes based on actual bandwidth requirements while maintaining consistent data throughput.

Ansys’ Caty Fairclough suggests using system architecture models to efficiently share information, ensure everyone is working on the latest design iteration, and confirm that safety criteria are being met throughout all design stages.

SEMI’s Maria Daniela Perez chats with Merck KGaA’s Kai Beckmann about the company’s acquisition of metrology tool provider Unity-SC and its broader strategy of combining expertise in semiconductors and optics.

Plus, check out the blogs featured in the latest Systems & Design newsletter:

Technology Editor Brian Bailey contends that predictions should be based on pain, not reflect innovation or breakthroughs.

Synopsys’ Almitra Pradhan explains how symbolic simulation can help avoid power leaks, power-ground DC paths, and missing level shifters.

Arteris’ Andy Nightingale digs into packet-based data transfer mechanisms and how they enable higher bandwidth, better routing optimization, and reduced congestion.

Keysight’s Jenn Mullen details ways to future-proof AI data center designs now that computational power has become the modern world’s most precious resource.

Eliyan’s Ramin Farjadrad and Syrus Ziai zero in on AI infrastructure efficiency gains versus the scale of personalization.

Alphawave Semi’s Letizia Giuliano contends that AI data center architectures require a new design approach.

Siemens’ John Ferguson and Lei Ling show how to identify and run only the design rules that are local in scope to reduce runtime and hardware requirements.

Cadence’s Vinod Khera explores how to accurately estimate yields and identify worst-case scenarios with fewer simulations and less time.

Keysight’s Brad Jolly finds the growing internet of medical things (IoMT) has unique definitions and testing requirements.